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| Number | Title | Issue Date |
| 5827761 | Method of making NMOS and devices with sequentially formed gates having different gate lengths A method of making NMOS and PMOS devices with different gate lengths includes providing a semiconductor substrate with first and second active regions, forming a first gate over a portion of the first active region and a second gate over a portion of the ... | 10/27/1998 |
| 5677224 | Method of making asymmetrical N-channel and P-channel devices An asymmetrical N-channel IGFET and an asymmetrical P-channel IGFET are disclosed. One or both IGFETs include a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region. Preferably, the heavily doped sou... | 10/14/1997 |
| 5648286 | Method of making asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region An asymmetrical IGFET including a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and heavily doped source region provide channel junctio... | 07/15/1997 |
| 5645469 | Polishing pad with radially extending tapered channels A polishing pad having a polishing surface with radially extending tapered channels is disclosed. The polishing surface includes an inner radius within an outer radius, and the channels extend from the inner radius to the outer radius. Preferably, the out... | 07/08/1997 |
