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| Number | Title | Issue Date |
| 6139199 | Fast just-in-time (JIT) scheduler A just-in-time (JIT) compiler typically generates code from bytecodes that have a sequence of assembly instructions forming a "template". It has been discovered that a just-in-time (JIT) compiler generates a small number, approximately 2.3, assembly instr... | 10/31/2000 |
| 6127261 | Method of fabricating an integrated circuit including a tri-layer pre-metal interlayer dielectric compatible with advanced CMOS technologies A method of depositing a premetal dielectric layer involves deposition of a triple premetal dielectric layer in in-situ deposition in a single fabrication tool with each subsequent layer being deposited after a previous layer with no intervening handling ... | 10/03/2000 |
| 6124179 | Inverted dielectric isolation process A method of semiconductor fabrication includes the steps of forming a dielectric layer on a first surface of a semiconductor wafer having a plurality of laterally distributed semiconductor devices selectively interconnected on the first surface and bondin... | 09/26/2000 |
| 6085278 | Communications interface adapter for a computer system including posting of system interrupt status To facilitate access of interrupt status information, interrupt posting status. POST-- STAT registers are readable by a host driver routine to quickly supply information relating to a functional block which has given rise to an interrupt status... | 07/04/2000 |
| 6046942 | Output buffer including an application-specific SRAM memory cell for low voltage, high speed operation An application-specific SRAM memory cell includes first and second cross-coupled inverters coupled at first and second nodes for storing a bit of information at the first node and a complement of the bit at the second node, first and second series-connect... | 04/04/2000 |
| 6032208 | Process control system for versatile control of multiple process devices of various device types A process controller implements smart field device standards and other bus-based architecture standards so that communications and control among devices are performed so that the standard control operations are transparent to a user. The process controlle... | 02/29/2000 |
| 6009479 | System and method for assigning unique addresses to agents on a system management bus A computer system including a bus master performs a method for automatically assigning addresses to agents on a bus. Addresses are automatically assigned so that a computer system user does not set physical or logical switches, either manually or through ... | 12/28/1999 |
| 6003129 | System and method for handling interrupt and exception events in an asymmetric multiprocessor architecture A multiprocessor computer system includes a plurality of processors, called asymmetric processors, having mutually dissimilar control and data-handling characteristics. The asymmetric processors are controlled by a single operating system although the ind... | 12/14/1999 |
| 6002801 | Method and apparatus for improved video decompression by selection of IDCT method based on image characteristics A video decoding system examines a block of DCT coefficients prior to computation of an inverse discrete cosine transform (IDCT) to determine the number of nonzero coefficients. A plurality of IDCT engines are available in the video system including an ID... | 12/14/1999 |
| 5996020 | Multiple level minimum logic network A network or interconnect structure utilizes a data flow technique that is based on timing and positioning of messages communicating through the interconnect structure. Switching control is distributed throughout multiple nodes in the structure so that a ... | 11/30/1999 |
| 5996067 | Range finding circuit for selecting a consecutive sequence of reorder buffer entries using circular carry lookahead A enable circuit (700), employing a "circular carry lookahead" technique to increase its speed performance, is provided for applying two pointers to a circular buffer--an enabling pointer (tail (218)) and a disabling pointer (head (216))--and ... | 11/30/1999 |
| 5996058 | System and method for handling software interrupts with argument passing A multiprocessor architectural definition provides that a program executing on a first processor interrupts a second processor by executing a software interrupt instruction. The software interrupt instruction includes an argument field for passing informa... | 11/30/1999 |
| 5995916 | Process control system for monitoring and displaying diagnostic information of multiple distributed devices A process control system includes a diagnostic monitoring and display functionality for viewing, in a coherent manner, diagnostic information relating to a process that operates over multiple devices and system components. Although the multiple devices an... | 11/30/1999 |
| 5991806 | Dynamic system control via messaging in a network management system A transactional event management structure is implemented in a network computer system. A dynamic system controller resolves proprietary and standard event and message structures into a common format for use by a system for many management purposes. A dyn... | 11/23/1999 |
| 5987557 | Method and apparatus for implementing hardware protection domains in a system with no memory management unit (MMU) A low overhead, efficient, and simple protection check circuit is inserted into a data path between a master requester and a target resource such as a memory or input/output device. The master requester initiates a memory request, a pio access request, or... | 11/16/1999 |
| 5986490 | Amplifier-based flip-flop elements A current-sensing static amplifier-based flip-flop is useful for high-performance VLSI circuitry. The flip-flop has a short latency and a small hold time, advantageous features in high-performance microprocessors. A flip-flop circuit includes an amplifier... | 11/16/1999 |
| 5983346 | Power-up initialization circuit that operates robustly over a wide range of power-up rates A power-up initialization circuit includes a transistor that generates a positive leakage current at the onset of a power-up ramp voltage. The positive leakage current drives a first node connected to a latch to a first defined state. The latch drives a c... | 11/09/1999 |
| 5976956 | Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device Dopant atoms have coefficients of diffusion that vary due to implant damage. Damaged regions are selected and created by implanting silicon atoms into a silicon substrate prior to formation of a gate electrode. The silicon atoms act as a getter for attrac... | 11/02/1999 |
| 5978903 | Apparatus and method for automatically accessing a dynamic RAM for system management interrupt handling A System Management Mode is transparent to normal system operations and dynamic RAM (DRAM) is available in the Upper Memory Block address range that is normally not accessible in many configurations. Therefore, the DRAM is advantageously used to attain Sy... | 11/02/1999 |
| 5969407 | MOSFET device with an amorphized source An amorphized implant is performed to retard diffusion of ions in the source and drain regions. By retarding the diffusion of ions in these regions, a shallower junction is advantageously created in the silicon regions of the wafer. A slight degradation i... | 10/19/1999 |
| 5965842 | Low impedance connection for an EMI containment shield including metal plating bonded to the shielded equipment through openings in a conductive ribbon The present invention provides an EMI shield having a low impedance connection to ground for use in electronic equipment, particularly computer systems. More particularly, an EMI shield for electronic equipment is disclosed which includes a conductive rib... | 10/12/1999 |
| 5964884 | Self-timed pulse control circuit A Self-Timed Pulse Control circuit and operating method is highly useful for adjusting delays of timing circuits to prevent logic races. In an illustrative example, the STPC circuit is used to adjust timing in self-timed sense amplifiers. The Self-Timed P... | 10/12/1999 |
| 5966312 | Method for monitoring and analyzing manufacturing processes using statistical simulation with single step feedback A statistical simulation of a semiconductor fabrication process is performed in parallel with the actual process. Input parameters derived from a probability density function are applied to the simulator which, in turn, simulates an actual fabrication pro... | 10/12/1999 |
| 5958054 | System and method for emulating an uninterruptable power supply (UPS) using a portable computer A portable computer including a chargeable battery and an AC line adapter controls the battery and adapter to emulate a full UPS-class device. A controller of the portable computer with the chargeable battery and the AC line adapter emulates the conventio... | 09/28/1999 |
| 5959468 | Buffer for static in/static out dynamic speed CMOS logic is coupled to dynamic logic which in turn is coupled to CMOS logic such than a clock is not required for the dynamic logic. Such a mixed static/dynamic buffer provides increased speed and fan-out. A buffer includes a dynamic circuit block coupl... | 09/28/1999 |
| 5953613 | High performance MOSFET with a source removed from the semiconductor substrate and fabrication method thereof The ultimate shallow source drain junction depth for a transistor is achieved by removing or detaching a source from the semiconductor substrate and forming an electron source on the surface of the semiconductor substrate adjacent to the transistor gate. ... | 09/14/1999 |
| 5950301 | Method for fabricating thin flim magnetic head including an elevated gap structure A thin film magnetic head is provided in which a magnetic yoke assembly is built up, layer by layer, atop a substrate using semiconductor thin film techniques. A lower yoke assembly is first fabricated including a lower magnetic layer situated on the subs... | 09/14/1999 |
| 5953457 | Method and apparatus for improved video decompression by prescaling of pixel and error terms to merging A video decoding apparatus and method greatly reduces the computational burden of video decoding by processing several pixels in parallel, thereby reducing the computational load by a factor approximating the number of pixels processed at one time.... | 09/14/1999 |
| 5949439 | Computing apparatus and operating method using software queues to improve graphics performance A software queue located in an offscreen portion of video memory is used as a large-capacity software queue for queuing messages to a graphics accelerator. Although the software queue is typically stored in a dynamic RAM (DRAM) memory, advantages of faste... | 09/07/1999 |
| 5949410 | Apparatus and method for synchronizing audio and video frames in an MPEG presentation system Synchronization of MPEG audio and video presentations is attained by detecting a lack of synchrony between the data presentations and modifying the audio data stream based on the detected lack of synchrony. Synchrony of the MPEG audio and video presentati... | 09/07/1999 |
| 5949092 | Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator A multi-dimensional transistor structure is fabricated which includes a base transistor substrate upon which transistors are formed. An elevated substrate is formed overlying the base transistor and having an oxide isolation formed in localized regions be... | 09/07/1999 |
| 5943550 | Method of processing a semiconductor wafer for controlling drive current Transistor drive current is controlled by controllably varying light exposure across a semiconductor substrate wafer based on an integrated circuit parameter. Integrated circuit parameters upon which the light exposure is varied include gate oxide thickne... | 08/24/1999 |
| 5940956 | Chemical-mechanical contouring (CMC) method for forming a contoured surface A method of fabricating thin film magnetic heads on a thin film substrate uses a chemical-mechanical contouring (CMC) step after completion of the fundamental thin film head structure to form a curved surface on the substrate for the individual thin film ... | 08/24/1999 |
| 5938845 | Uniform heat distribution apparatus and method for electroless nickel plating in fabrication of thin film head gaps An electroless plating apparatus heats a plating bath solution with precise uniformity and avoids localized high temperatures within the bath. The electroless plating apparatus achieves this performance using two solution tanks included an inner tank nest... | 08/17/1999 |
| 5930838 | Pant garment having an opening optimized for the female anatomy A pant or short garment has a female body crotch opening in the crotch region of the garment. The crotch opening is covered by a removable saddle flap which is firmly affixed to the seat of the garment and is attachable at the inner left and right leg reg... | 08/03/1999 |
| 5933717 | Vertical transistor interconnect structure and fabrication method thereof It has been discovered that improvements in the compactness and performance of integrated circuit devices are gained through the fabrication of vertical transistors for which channel sizes are determined by the accuracy of etch techniques rather than the ... | 08/03/1999 |
| 5933594 | Diagnostic system for run-time monitoring of computer operations A monitoring system is coupled to an external computer system by an interface between a data bus internal to the monitoring system and a target bus within the external computer system. Data captured by the monitoring system from the external computer syst... | 08/03/1999 |
| 5926690 | Run-to-run control process for controlling critical dimensions It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated ... | 07/20/1999 |
| 5918129 | Method of channel doping using diffusion from implanted polysilicon A method of doping an integrated circuit device channel in a semiconductor substrate laterally enclosed by an isolation structure is disclosed. The method includes steps of forming a thin oxide layer overlying the integrated circuit device channel and the... | 06/29/1999 |
| 5918126 | Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size It has been discovered that different pattern densities that occur in conventional lithography produce a different final etch polysilicon gate width in high density (dense) regions of polysilicon gates as compared to low density (isolated) polysilicon gat... | 06/29/1999 |
