Bizarre Patents
Neuroimaging as a Marketing Tool
Neuroimaging as a means for validating whether a stimulus such as advertisement, communication, or product evokes a certain mental response such as emotion, preference, or memory, or to predict the consequences of the stimulus on later behavior such as consumption or purchasing.
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| Number | Title | Issue Date |
| 6200736 | Photoresist developer and method An interrupted development, multi-cycle development process, in combination with an aqueous photoresist developer composition enables development of electron-beam exposed novolak-resin based photoresists with resolution of less than 0.20 μm, contrast >5,... | 03/13/2001 |
| 6157039 | Charged particle beam illumination of blanking aperture array A charged particle beam column efficiently illuminates a blanking aperture array by splitting a charged particle beam into multiple charged particle beams and focusing each charge particle beam on a separate aperture of the blanking aperture array. Where ... | 12/05/2000 |
| 6154064 | Differential sense amplifier circuit A sense amplifier having four NMOS transistors and two resistors is operable at voltage supplies less than 2.5 volts and has a fast response time. The drain terminals of two of the NMOS transistors, each receiving an input voltage signal at its gate termi... | 11/28/2000 |
| 6150962 | Predictive data entry method for a keyboard A predictive data entry method permits a user of a device to efficiently enter data using a keypad where each of a plurality of keys represents a plurality of different characters. When the user presses one of the keys representing multiple characters, th... | 11/21/2000 |
| 6144844 | Method and system for controlling frequency A method and system for receiving a signal in a received frequency and shifting the received frequency to become a desired frequency is provided. The system includes a controllable oscillator for generating a first internal frequency, a frequency estimati... | 11/07/2000 |
| 6137686 | Interchangeable modular arrangement of computer and accessory devices A structure wherein a hand held computer module can be conveniently and interchangeably coupled to accessory devices. The hand held computer module is detachably connected to a first accessory module by a first interlocking structure. The computer module ... | 10/24/2000 |
| 6127738 | Detecting registration marks with low energy electron beam For electron beam wafer or mask processing, a registration mark is capacitively coupled to the top surface of an overlying resist layer on a substrate to form a voltage potential on the surface of the resist layer directly over the registration mark. The ... | 10/03/2000 |
| 6103845 | Chemically amplified resist polymers Copolymers and terpolyers are used in chemically amplified resists. The terpolymers are of the formula: ##STR1## wherein R3 is selected from the group consisting of hydrogen and a C1 to C10 aliphatic hydrocarbon, wher... | 08/15/2000 |
| 6063676 | Mosfet with raised source and drain regions A semiconductor substrate having a surface, a field oxide region at the surface and a gate structure above the surface are provided. A sidewall spacer is formed adjacent to the gate structure and a polysilicon layer is formed above the substrate, the poly... | 05/16/2000 |
| 6043129 | High density MOSFET with raised source and drain regions A semiconductor substrate having a surface, a planarized field oxide region at the surface and a gate structure overlying the surface are provided. A sidewall spacer is formed adjacent to the gate structure and a polysilicon layer is formed overlying the ... | 03/28/2000 |
| 6023529 | Handwritten pattern recognizer with selective feature weighting A handwritten pattern recognition system for recognizing an input pattern is provided. The system has a plurality of parameter determining units, each determining the value of a desired parameter for an input pattern to be recognized. The system also incl... | 02/08/2000 |
| 5997174 | Method for determining a thermal parameter of a device by measuring thermal resistance of a substrate carrying the device The junction temperature of a die inside an electronic component is empirically determined by use of a board simulator that simulates a target board on which the electronic component is to be operated. The board simulator's thermal resistivity is determin... | 12/07/1999 |
| 5987031 | Method for fair dynamic scheduling of available bandwidth rate (ABR) service under asynchronous transfer mode (ATM) A method for dynamic scheduling of data transmission for a large number of data channels under the available bit rate (ABR) service protocols of asynchronous transfer mode (ATM) uses a schedule table and ready queue. In this method, at each time slot, dat... | 11/16/1999 |
| 5982699 | Parallel write logic for multi-port memory arrays In a traditional multi-port memory, the writing of a memory cell is performed only by the single port which is enabled for writing. Row contention occurs when other ports access the same memory cell, such as when ports share the same row address, and when... | 11/09/1999 |
| 5968193 | Dual site loadboard tester A method and apparatus for testing integrated circuit devices includes a dual site loadboard (60) with dual test sites (62) for holding integrated circuit devices. The dual test sites are connected to test instruments. Integrated circuit devices are loade... | 10/19/1999 |
| 5966035 | High voltage tolerable input buffer An input buffer includes an n-channel FET having a drain region coupled to the Vcc voltage supply, a source region coupled to the output terminal and a gate electrode coupled to the input terminal. A bias circuit maintains a voltage at the sour... | 10/12/1999 |
| 5962924 | Semi-conductor die interconnect An improved flip-chip bond connection and bonding method uses a "press fit" bond between a set of bond pad bumps or projections on a semiconductor chip and corresponding set of substrate bumps or projections on a substrate to self-align the chip with the ... | 10/05/1999 |
| 5957370 | Plating process for fine pitch die in wafer form Apertures in a tape formed on a substrate allow straight plating of solder bumps to heights above 4 mils. The solder bumps are combined with a lower density material to form an hourglass-shaped structure which allows interconnections to bonding pads of el... | 09/28/1999 |
| 5956234 | Method and structure for a surface mountable rigid-flex printed circuit board A method and structure for a surface mountable rigid-flex printed circuit board is disclosed. A rigid-flex circuit board is mounted onto a printed circuit board using standard surface mount technology such as ball grid array, pin grid array or solder scre... | 09/21/1999 |
| 5949127 | Electrically programmable interlevel fusible link for integrated circuits In a multi-level interconnect structure, a fusible material fills an opening in an isolation layer disposed between two interconnect levels or between an interconnect level and a device layer. The opening which may be, for example, a contact hole or a via... | 09/07/1999 |
| 5939762 | SRAM cell using thin gate oxide pulldown transistors The pulldown transistors of an SRAM cell are made to have higher threshold voltages and thinner gate insulating layers than the access transistors of the cell. In some embodiments, this allows a reduced supply voltage Vcc (for example, 3.3 volts) to be us... | 08/17/1999 |
| 5936608 | Computer system including display control system A computer system and methodology for controlling the brightness of visual objects displayed on an electron beam flat panel display monitor used in a computer system having a multitasking operating system and a graphics controller coupled to the display m... | 08/10/1999 |
| 5931580 | Apparatus for measuring junction temperature The junction temperature of a die inside an electronic component is empirically determined by use of a board simulator that simulates a target board on which the electronic component is to be operated. The board simulator includes a thermoelectric cooler ... | 08/03/1999 |
| 5923577 | Method and apparatus for generating an initial estimate for a floating point reciprocal An initial estimate of a reciprocal of a floating point number is generated in one addition having correct sign, exponent and up to five or more bits of precision in the fraction by subtracting the input floating point number from a constant. The constant... | 07/13/1999 |
| 5911108 | Method for protecting an alignment mark on a semiconductor substrate during chemical mechanical polishing and the resulting structure A method for maintaining an alignment mark on a semiconductor substrate includes formation of an opening called a "protective window," that is sufficiently deep to ensure that an alignment mark formed at the bottom of the preventive window remains intact ... | 06/08/1999 |
| 5903618 | Multimode radio communication system Like a conventional one-way pager system, a two-way pager system is provided in which a message is received by paging from a base station and a message responding to the received message is returned to the base station. In this system, direct communicatio... | 05/11/1999 |
| 5894176 | Flexible reset scheme supporting normal system operation, test and emulation modes A structure and a method are provided to implement a reset scheme for an integrated circuit supporting a variety of testing and debugging equipment. The control and I/O pins of the integrated circuit are each set to a high impedance state when the signals... | 04/13/1999 |
| 5888861 | Method of manufacturing a BiCMOS integrated circuit fully integrated within a CMOS process flow A process for manufacturing a BiCMOS integrated circuit is implemented by adapting the masking and doping steps used in forming CMOS devices. Thus simultaneous formation of both CMOS and bipolar device structures eliminates the need for any additional mas... | 03/30/1999 |
| 5875151 | Fully synchronous pipelined ram A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write d... | 02/23/1999 |
| 5875267 | Fast digital image sharpening method and structure An initial digital image is blurred to form a blurred image which is subtracted from the initial image in order to form a sharpened version of the initial image. Unidirectional blurs provide for blurring the initial image, wherein the value of each pixel ... | 02/23/1999 |
| 5871621 | Method of fabricating a textured magnetic storage disk A magnetic disk storage medium (10) includes a smooth non-magnetic substrate (11) having surface roughened by sputter-depositing a continuous nonmagnetic rough thin film ("texture film") (14) over the substrate. The sputter conditions and composition of t... | 02/16/1999 |
| 5867672 | Triple-bus FIFO buffers that can be chained together to increase buffer depth A buffer IC includes two FIFO buffers accessible in a triple-bus configuration including a bi-directional port, an input port, and an output port. Each of the ports uses a fall-through timing which facilitates interconnection of similar buffer ICs into a ... | 02/02/1999 |
| 5867682 | High performance superscalar microprocessor including a circuit for converting CISC instructions to RISC operations A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer,... | 02/02/1999 |
| 5844887 | ATM switching fabric A distributed, scalable and modular asynchronous transfer mode (ATM) switching fabric is disclosed. The switching fabric includes port interface modules for connecting physical devices to the switch fabric. The switch fabric is arranged as rows of input b... | 12/01/1998 |
| 5841165 | PMOS flash EEPROM cell with single poly A P-channel single-poly EPROM cell has P+ source and P+ drain regions, and a channel extending therebetween, formed in an N-type well. A thin layer of tunnel oxide is provided over the channel and, in some embodiments, over significant portions of P+ sour... | 11/24/1998 |
| 5838622 | Reconfigurable multiplexed address scheme for asymmetrically addressed DRAMs A long X bit or a long Y bit is stored in a latch and used to supplement the Y address bits in an asymmetric DRAM memory thereby to allow one part to be used for a design requiring a long X bit and also for a design requiring a long Y bit.... | 11/17/1998 |
| 5834125 | Non-reactive anti-reflection coating An anti-reflection coating is provided that has a barrier layer and an anti-reflective layer. The barrier layer stops reactions between the anti-reflective layer and underlying layers or substrates, does not make the anti-reflective layer reflective, and ... | 11/10/1998 |
| 5834859 | Battery backed configurable output buffer The present invention is a battery backed output buffer which provides a well-defined signal, even during battery power. The buffer includes a regular output buffer for providing output data during operation with a main power supply and for switching to a... | 11/10/1998 |
| 5828606 | Fully synchronous pipelined RAM A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write d... | 10/27/1998 |
| 5828623 | Parallel write logic for multi-port memory arrays In a traditional multi-port memory, the writing of a memory cell is performed only by the single port which is enabled for writing. Row contention occurs when other ports access the same memory cell, such as when ports share the same row address, and when... | 10/27/1998 |
