"I think there is a world market for maybe five computers."
Thomas Watson, chairman of IBM ; 1943
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| Number | Title | Issue Date |
| 6384910 | Sample inspection system A curved mirrored surface is used to collect radiation scattered by a sample surface and originating from a normal illumination beam and an oblique illumination beam. The collected radiation is focused to a detector. Scattered radiation originating from t... | 05/07/2002 |
| 6381683 | Method and system for destination-sensitive memory control and access in data processing systems A method and system providing a memory controller having a destination-sensitive memory request reordering device. The destination-sensitive memory request reordering device includes a centralized state machine operably connected to one or more memory dev... | 04/30/2002 |
| 6381603 | System and method for accessing local information by using referencing position system A system and method for accessing local information in a database. The database is organized with merchandise information including identifier of information provider, identifier information, position information, and description information. The position... | 04/30/2002 |
| 6350645 | Strapping via for interconnecting integrated circuit structures A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a cont... | 02/26/2002 |
| 6343072 | Single-chip architecture for shared-memory router The invention provides a single-chip method. The method includes a memory shared among packet buffers for receiving packets, packet buffers for transmitting packets, and packet header buffers for packet forwarding lookup. Accesses to that shared memory ar... | 01/29/2002 |
| 6333524 | Electrically programmable interlevel fusible link for integrated circuits In a multi-level interconnect structure, a fusible material fills an opening in an isolation layer disposed between two interconnect levels or between an interconnect level and a device layer. The opening which may be, for example, a contact hole or a via... | 12/25/2001 |
| 6317349 | Non-volatile content addressable memory A content addressable memory (CAM) includes non-volatile CAM cells that are in an array similar to a conventional Flash memory array. In the CAM, each word line connects to control gates of Flash memory cells in a row, each bit line connects to drains of ... | 11/13/2001 |
| 6307399 | High speed buffer circuit with improved noise immunity In a buffer circuit a pull-up circuit causes an output terminal of the buffer circuit make a transition from a low voltage to a high, and a feedback circuit increases the rate of the transition during the part of the transition when the output terminal mo... | 10/23/2001 |
| 6306771 | Process for preventing the formation of ring defects The prevention of the formation of undesired defects formed during the etching of etched metal interconnect lines on an integrated circuit during an integrated circuit manufacturing process that involves laying down on a semiconductor wafer a thin film su... | 10/23/2001 |
| 6304196 | Disparity and transition density control system and method A system and method for encoding and decoding data utilizes Walsh-Hadamard Transforms and inversion techniques to generate the possible minimum disparity values for the data to be encoded. A minimum disparity value is then selected that also provides suff... | 10/16/2001 |
| 6262562 | Increased battery capacity utilizing multiple smart batteries A method for allowing a data processing system to use multiple smart batteries substantially simultaneously coupled to the same smart bus, the method including but not limited to detecting at least two smart batteries connected to a smart battery bus; and... | 07/17/2001 |
| 6260123 | Method and system for memory control and access in data processing systems It has been discovered that a method and system can be produced which will, among other things, provide data processing systems having memory controllers with the ability to look ahead and intelligently schedule accesses to system memory. A method and sys... | 07/10/2001 |
| 6258693 | Ion implantation for scalability of isolation in an integrated circuit Implanted regions, formed in a semiconductor substrate by ion implanting oxygen or nitrogen ions, are converted to dielectric isolation regions by high temperature annealing. In some embodiments, oxygen and/or nitrogen ions are implanted at multiple prede... | 07/10/2001 |
| 6252161 | EMI shielding ventilation structure A data processing system including but not limited to an enclosure of the data processing system having a waveguide-below-cutoff EMI-attenuating air ventilation structure formed from a dielectric-conductor combination material, the enclosure of the data p... | 06/26/2001 |
| 6243779 | Noise reduction system and method for reducing switching noise in an interface to a large width bus A method of communicating a data word via a bus includes driving the data word onto the bus in whichever one of a true polarity form and a complement polarity form that requires fewer bus lines to change state relative to a present state of each bus line,... | 06/05/2001 |
| 6243612 | Processing system having a scheduling system based on a composite ratio of process scheduling factors A processing system includes a scheduling system to scheduling processing of lots which are distributed among various processing system stations. Process scheduling is determined in accordance with lot specific composite ratios which are a function of pro... | 06/05/2001 |
| 6226721 | Method and system for generating and utilizing speculative memory access requests in data processing systems A method and system for generating and utilizing speculative memory accesses in data processing systems. The method and system provide a memory controller having at least one origin-sensitive speculative memory access request generator. The origin-sensiti... | 05/01/2001 |
| 6222396 | Electronic system having a multistage low noise output buffer system In one embodiment, a multistage output buffer supplies current to a load by successively turning ON output buffer circuits which transition from an OFF state to approximately a saturated state during approximately mutually exclusive periods of time. Thus,... | 04/24/2001 |
| 6219769 | Method and system for origin-sensitive memory control and access in data processing systems A method and system which improve data processing system memory access. The method and system provide a memory controller having an origin-sensitive memory request reordering device. The origin-sensitive memory request reordering device includes one or mo... | 04/17/2001 |
| 6219642 | Quantization using frequency and mean compensated frequency input data for robust speech recognition A speech recognition system utilizes multiple quantizers to process frequency parameters and mean compensated frequency parameters derived from an input signal. The quantizers may be matrix and vector quantizer pairs, and such quantizer pairs may also fun... | 04/17/2001 |
| 6216239 | Testing method and apparatus for identifying disturbed cells within a memory cell array A method and structure for identifying disturbed memory cells within a memory cell array are provided. A test circuit consists of several cells within the memory cell array, and are coupled to the cells in the memory cell array. The test cells are also co... | 04/10/2001 |
| 6215668 | Expansion card retaining device An expansion card retention system and method. In one embodiment, the expansion card retention system includes an expansion card retaining unit which has a vertical axis, an extended member, and a vertical-axis extended member pressure application device ... | 04/10/2001 |
| 6212607 | Multi-ported memory architecture using single-ported RAM A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0~401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0~405-7, 406-0~406-7... | 04/03/2001 |