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| Number | Title | Issue Date |
| 7149991 | Calibrating a wire load model for an integrated circuit A method is taught for determining a calibrated wire load model. The calibrated wire load model can be used to reach timing closure for an integrated circuit. The method includes; determining a reference timing description; determining a wire load model based on syn... | 12/12/2006 |
| 7053419 | Light emitting diodes with improved light extraction efficiency Light emitting devices with improved light extraction efficiency are provided. The light emitting devices have a stack of layers including semiconductor layers comprising an active region. The stack is bonded to a transparent lens having a refractive index for light... | 05/30/2006 |
| 6992725 | Video data de-interlacing using perceptually-tuned interpolation scheme A de-interlacing architecture is taught. The de-interlacing architecture adopts a perceptual model to measure membership probabilities for a collection of image samples of an interlaced video source with respect to extracted static, motion, and texture image compone... | 01/31/2006 |
| 6985843 | Cell modeling in the design of an integrated circuit The invention relates to a method for modeling an input/output cell located on the perimeter of an integrated circuit. A method is taught to model an the integrated circuit when sufficient area is not available on the perimeter of the integrated circuit. The input/o... | 01/10/2006 |
| 6859508 | Four dimensional equalizer and far-end cross talk canceler in Gigabit Ethernet signals A multidimensional equalizer and cross talk canceller for a communication network that simultaneously removes far end cross talk NEXT) and intersymbol interference (ISI) from a received signal. A multidimensional-pair channel is treated as a single multidimensional ... | 02/22/2005 |
| 6782502 | Combinational test pattern generation method and apparatus A method and apparatus that couple a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic pa... | 08/24/2004 |
| 6766212 | Identifying relationships among constituent parts of a wafer fabrication system A method and system for use in wafer fabrication systems. The method and system identify relationships among constituent parts of a wafer fabrication system by generating a presentation of at least one relationship between an identified at least one integral part as... | 07/20/2004 |
| 6728590 | Identifying wafer fabrication system impacts resulting from specified actions A method and system for use in wafer fabrication systems. The method and system identify wafer fabrication system impacts resulting from specified actions by specifying at least one action related to at least one integral part associated with the wafer fabrication s... | 04/27/2004 |
| 6715040 | Performance improvement of a write instruction of a non-inclusive hierarchical cache memory unit Described is a data processing system including a processor, a plurality of caches, and main memory, the secondary caches being implemented as being non-inclusive, i.e., the lower order caches not storing a superset of the data stored in the next higher order cache.... | 03/30/2004 |
| 6627901 | Apparatus and method for distribution of dopant gases or vapors in an arc chamber for use in an ionization source An apparatus and method for distributing dopant gas or vapor in an arc chamber of ion source used as part of an ion implanter. The apparatus includes a plenum, a sub-plenum, and a baffle to distribute the dopant gas or vapor through out the arc chamber. T... | 09/30/2003 |
| 6625781 | Multi-level power macromodeling The invention utilizes the linear complexity of orthogonal vectors to reduce the number of equations (or variables) to be solved. The present invention constructs a power model of a set of combinations of states without considering irrelevant combinations... | 09/23/2003 |
| 6622283 | Digital signal processor decoding of convolutionally encoded symbols In one embodiment, a file of all the initial states (or their equivalents) and the nth surviving states associated with the initial states is stored along with the path metric. The initial states (or their equivalents) are an index to a previous file. A.n... | 09/16/2003 |
| 6593653 | Low leakage current silicon carbonitride prepared using methane, ammonia and silane for copper diffusion barrier, etchstop and passivation applications A silicon carbon nitride (SiCN) layer is provided which has a low leakage current and is effective in preventing the migration or diffusion of metal or copper atoms through the SiCN layer. The SiCN layer can be used as a diffusion barrier between a metal ... | 07/15/2003 |
| 6590645 | System and methods for classifying anomalies of sample surfaces Two or more defect maps may be provided for the same sample surface at different detection sensitivities and/or processing thresholds. The defect maps may then be compared for better characterization of the anomalies as scratches, area anomalies or point ... | 07/08/2003 |
| 6589801 | Wafer-scale production of chip-scale semiconductor packages using wafer mapping techniques A method is disclosed for manufacturing chip-scale semiconductor packages at a wafer-scale level using wafer mapping techniques. In the method, a semiconductor wafer and/or a circuit substrate, each respectively comprising a plurality of individual chips ... | 07/08/2003 |
| 6570790 | Highly compact EPROM and flash EEPROM devices Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangemen... | 05/27/2003 |
| 6570662 | Optical techniques for measuring layer thicknesses and other surface characteristics of objects such as semiconductor wafers A characteristic of a surface is measured by illuminating the surface with optical radiation over a wide angle and receiving radiation reflected from the surface over a wide angle. An emissivity measurement can then be made for the surface, and, alternati... | 05/27/2003 |
| 6562204 | Apparatus for potential controlled electroplating of fine patterns on semiconductor wafers Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed ... | 05/13/2003 |
| 6560749 | Apparatus and method for implementing a decoder for convolutionally encoded symbols An apparatus and method for implementing a decoder for convolutionally encoded symbols (e.g., a viterbi decoder) is described. In one embodiment, a file of all the initial states (or their equivalents) and the nth surviving states associated with the init... | 05/06/2003 |
| 6560143 | Method and structure for efficient data verification operation for non-volatile memories An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a seco... | 05/06/2003 |
| 6558253 | Slot machine with award multiplier display A slot machine is described which allows a player to participate in an additional game of chance whenever a winning combination of symbols includes a special bonus multiplier symbol. In such instances, the award for the winning combination is multiplied b... | 05/06/2003 |
| 6553402 | Method for coordinating activities and sharing information using a data definition language A widely-used data definition language such as the Extensible Markup Language is used to implement a tuple space-based coordination mechanism. Entries and template entries can represent any type of networked or network-proxied resource, object or service.... | 04/22/2003 |
| 6552410 | Programmable antifuse interfacing a programmable logic and a dedicated device A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicate... | 04/22/2003 |
| 6551483 | Method for potential controlled electroplating of fine patterns on semiconductor wafers Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed ... | 04/22/2003 |
| 6551403 | Solvent pre-wet system for wafers A system for improving manufacture, said system including but not limited to a Polyimide solvent dispensing nozzle proximate to a Polyimide dispensing nozzle. In one embodiment, the Polyimide solvent dispensing nozzle proximate to a Polyimide dispensing n... | 04/22/2003 |
| 6549456 | Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog volta... | 04/15/2003 |
| 6542956 | Latched address multi-chunk write to EEPROM An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associa... | 04/01/2003 |
| 6542407 | Techniques of recovering data from memory cells affected by field coupling with adjacent memory cells Techniques of overcoming a degradation of the apparent charge levels stored in one row of memory cells as a result of subsequently programming an adjacent row of memory cells. After storing the data of the subsequently programmed row elsewhere, the charge... | 04/01/2003 |
| 6542096 | Serializer/deserializer embedded in a programmable device In accordance with the invention, a serializer/deserializer core of a field programmable gate array includes a channel clock and a data channel. The data channel can serialize and deserialize data in two modes. In the first mode, an embedded clock signal ... | 04/01/2003 |
| 6541400 | Process for CVD deposition of fluorinated silicon glass layer on semiconductor wafer An improved process for depositing a robust fluorosilicate glass film on a substrate in a chamber includes maintaining a total pressure in the chamber of less than about 1.7 torr, introducing vapor phase chemicals such as N2, SiF4, S... | 04/01/2003 |
| 6539890 | Multiple source deposition plasma apparatus An apparatus for forming a film on a substrate includes a gas inlet and an insert attached to the gas inlet, the insert including a deposition source material such as lithium. To form the film on the substrate, the substrate is mounted in a vacuum chamber... | 04/01/2003 |
| 6539518 | Autodisk controller A device controller having an autodisk controller is presented. The autodisk controller in monitor mode is capable of monitoring the address of incoming data blocks and, when a target address is reached, triggers a switch of the device controller to buffe... | 03/25/2003 |
| 6538922 | Writable tracking cells The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written,... | 03/25/2003 |
| 6538730 | Defect detection system Scattered radiation from a sample surface is collected by means of a collector that collects radiation substantially symmetrically about a line normal to the surface. The collected radiation is directed to channels at different azimuthal angles so that in... | 03/25/2003 |
| 6538516 | System and method for synchronizing multiple phase-lock loops or other synchronizable oscillators without using a master clock signal A system and method for synchronizing a plurality of synchronizable oscillators are disclosed. The method includes monitoring a respective output signal of each synchronizable oscillator, each output signal having a respective frequency, generating a sync... | 03/25/2003 |
| 6535443 | Reduction of standby current The rate of discharge of the sense amplifier and bit lines in a memory circuit is controlled to simulate a boosted sense ground potential without requiring the use of a voltage regulator or precharged capacitors. The sense amplifier is electrically couple... | 03/18/2003 |
| 6534423 | Use of inductively-coupled plasma in plasma-enhanced chemical vapor deposition reactor to improve film-to-wall adhesion following in-situ plasma clean An inductively-coupled hydrogen plasma (ICP) is used to passivate a plasma-enhanced chemical vapor deposition reactor following an in situ cleaning step. The hydrogen ICP effectively removes the fluorine and hydrogen that typically become impregnated in t... | 03/18/2003 |
| 6534422 | Integrated ESD protection method and system An ESD structure is created on an integrated circuit by providing a conductive polymer material between a signal line and a supply node or ground reference. The conductive polymer material becomes conductive when an electric field of sufficient intensity ... | 03/18/2003 |
| 6534404 | Method of depositing diffusion barrier for copper interconnect in integrated circuit Diffusion barriers are used in integrated circuits. The present method of depositing diffusion barriers eliminates the formation of high resistivity phases, providing high electrical conductivity and diffusion suppression between the interconnect conducto... | 03/18/2003 |
| 6534366 | Method of fabricating trench-gated power MOSFET A trench-gated power MOSFET contains a highly doped region in the body region which forms a PN junction diode with the drain at the center of the MOSFET cell. This diode has an avalanche breakdown voltage which is lower than the breakdown voltage of the d... | 03/18/2003 |
