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| Number | Title | Issue Date |
| 8141014 | System and method for common history pessimism relief during static timing analysis A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and e... | 03/20/2012 |
| 8141012 | Timing closure on multiple selective corners in a single statistical timing run An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions. Re... | 03/20/2012 |
| 8108816 | Device history based delay variation adjustment during static timing analysis A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a... | 01/31/2012 |
| 7853443 | Transient simulation using adaptive piecewise constant model A transient simulation system, methods and program product that implement an adaptive piecewise constant (PWC) model are disclosed. The invention evaluates an error criteria to determine a maximum allowable change in one of a current and a voltage; and simulates the... | 12/14/2010 |
| 7803644 | Across reticle variation modeling and related reticle Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying a measurement structure for performing the test; implementing the mea... | 09/28/2010 |
| 7784000 | Identifying sequential functional paths for IC testing methods and system A method and system of identifying sequential functional paths for IC testing methods are disclosed. In one embodiment, a method may include a method of sequential functional path identification for at-speed structural test, the method comprising: using a timing too... | 08/24/2010 |
| 7783466 | IC chip parameter modeling A method and system are disclosed for preserving measured temperature and geometric behavior of a hardware model while adjusting the model to match specified target values. In one embodiment, the method includes measuring a characteristic of an integrated circuit (I... | 08/24/2010 |
| 7781292 | High power device isolation and integration A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, ... | 08/24/2010 |
| 7777302 | Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structure A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method includes forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilic... | 08/17/2010 |
| 7761821 | Technology migration for integrated circuits with radical design restrictions A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach th... | 07/20/2010 |
| 7761818 | Obtaining a feasible integer solution in a hierarchical circuit layout optimization An approach that obtains a feasible integer solution in a hierarchical circuit layout optimization is described. In one embodiment, a hierarchical circuit layout and ground rule files are received as input. Constraints in the hierarchical circuit layout are represen... | 07/20/2010 |
| 7752589 | Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern. ... | 07/06/2010 |
| 7750648 | Method to quickly estimate inductance for timing models A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field a... | 07/06/2010 |
| 7738984 | System for and method of interpolation for supply chain planning A method of iterative negotiation for improved production planning between one or more purchasers and suppliers in a supply chain. The method includes a purchaser in a supply chain generating a request schedule that is communicated to a supplier. In response to the ... | 06/15/2010 |
| 7735042 | Context aware sub-circuit layout modification A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are de... | 06/08/2010 |
| 7721240 | Systematic yield in semiconductor manufacture Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tende... | 05/18/2010 |
| 7712057 | Determining allowance antenna area as function of total gate insulator area for SOI technology A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulat... | 05/04/2010 |
| 7711534 | Method and system of design verification A method and system comprises extracting resources required to run a discrete test case or set of associated test cases on a design. The method and system further includes building a simulation model based on the extracted resources and executing the simulation mode... | 05/04/2010 |
| 7703061 | IC design modeling allowing dimension-dependent rule checking A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals... | 04/20/2010 |
| 7703053 | Regional pattern density determination method and system A method and system of determining a localized measure of regional pattern density in a fabrication process of a chip are disclosed. In one embodiment, the method includes determining pattern density values for each cell of a plurality of cells of interest; averagin... | 04/20/2010 |
| 7685544 | Testing pattern sensitive algorithms for semiconductor design A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout desi... | 03/23/2010 |
| 7681153 | Estimating static power consumption of integrated circuits using logic gate templates A method, system and computer program product for estimating a static power consumption of an integrated circuit are disclosed. The static power consumption of a cell of the integrated circuit is characterized based on contributions of an input node(s) and an output... | 03/16/2010 |
| 7650601 | Operating system kernel-assisted, self-balanced, access-protected library framework in a run-to-completion multi-processor environment A method for managing multiple processors in the execution of one or more processes in a task-based library platform. The one or more processes are partitioned into highly granulized sub-tasks from a library calling process, whereby each sub-task has a protection at... | 01/19/2010 |
| 7620921 | IC chip at-functional-speed testing with process coverage evaluation Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, ... | 11/17/2009 |
| 7606742 | Pre-processor for inbound sales order requests with link to a third party available to promise (ATP) system A method and apparatus for pre-processing electronic data requests within the EDI subsystem layer and within the order fulfillment application system. An order interceptor, third-party Available To Promise (ATP) interface, pseudo-sales order workbench, and the rejec... | 10/20/2009 |
| 7584077 | Physical design characterization system A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed throug... | 09/01/2009 |
| 7577927 | IC design modeling allowing dimension-dependent rule checking A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals... | 08/18/2009 |
| 7568173 | Independent migration of hierarchical designs with methods of finding and fixing opens during migration Methods of independently migrating a hierarchical design are disclosed. A method for migrating a macro in an integrated circuit comprises: determining an interface strategy between a base cell in the macro and the macro, the base cell including an interface element ... | 07/28/2009 |
| 7567948 | Method and system for obtaining a combination of faulty parts from a dispersed parts tree It is an object of the present invention to find out parts to be a highly possible cause of failure without searching all of part data of all of products. Dispersed parts data on a parts tree are sequentially accessed from a set of known failed products, and ... | 07/28/2009 |
| 7555740 | Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of... | 06/30/2009 |
| 7555735 | IC design modeling allowing dimension-dependent rule checking A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals... | 06/30/2009 |
| 7543252 | Migration of integrated circuit layout for alternating phase shift masks Method, system and program product for migrating an integrated circuit (IC) layout for, for example, alternating aperture phase shift masks (AltPSM), are disclosed. In order to migrate a layout to phase compliance, jogs are identified on a first (AltPSM) layer and s... | 06/02/2009 |
| 7526544 | Message tracking method, apparatus, and system A message tracker having a transfer monitor, a set of registers, and at least one arithmetic unit increases performance and reliability when transmitting or receiving messages within a computer system. A set of message parameters such as a current address, a remaini... | 04/28/2009 |
| 7496874 | Semiconductor yield estimation A method, apparatus, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis perform... | 02/24/2009 |
| 7490303 | Identifying parasitic diode(s) in an integrated circuit physical design A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to ... | 02/10/2009 |
| 7464217 | Design structure for content addressable memory A design structure for content addressable memory including a first array of memory cells, and a second array of memory cells. A search logic circuit is configured to prevent a discharge of the second array of memory cells when a search of the first array of memory ... | 12/09/2008 |
| 7464400 | Distributed environment controlled access facility A computer implemented web based access control facility for a distributed environment, which allows users to request for access, take the request through appropriate approval work flow and finally make it available to the users and applications. This program also p... | 12/09/2008 |
| 7454721 | Method, apparatus and computer program product for optimizing an integrated circuit layout A method, apparatus, and computer program product for optimizing the layout of an integrated circuit design. Base ground rules and recommended ground rules are prioritized according to the impact they have on the yield of the integrated circuit design. The layout is... | 11/18/2008 |
| 7451070 | Optimal bus operation performance in a logic simulation environment Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable re... | 11/11/2008 |
| 7360138 | Verification of the design of an integrated circuit background A method, apparatus, and computer program product for performing verification on an integrated circuit design having state variables. Random vectors are generated, used to simulate the design, and generate a set of values for the state variables. The generated value... | 04/15/2008 |
