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An aircraft having vertical takeoff and landing capability provided with at least first and second laterally extending paddle wheels rotatable on a central axis perpendicular to the longitudinal axis of the aircraft fuselage and between its nose and tail.
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| Number | Title | Issue Date |
| 8143855 | Rechargeable split battery system A battery system is split into first and second battery subsystems. When the first battery subsystem reaches a first discharge level, the first battery system is decoupled from output terminals of the battery system and the second battery subsystem is coupled to the... | 03/27/2012 |
| 8089298 | Integrated circuit device with dynamically selected on-die termination In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations. A termination ... | 01/03/2012 |
| 8078593 | Dictionary architecture and methodology for revision-tolerant data de-duplication Redundant data is removed from a volume of data by partitioning the volume of data into fixed-length input segments and, for each of the input segments, traversing nodes of a search tree in accordance with the value of a fixed-size portion of the input segment to de... | 12/13/2011 |
| 8059476 | Control component for controlling a delay interval within a memory component Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodic... | 11/15/2011 |
| 8045407 | Memory-write timing calibration including generation of multiple delayed timing signals A memory controller with multiple delayed timing signals. Control information is provided by a first output driver circuit to a first signal path. Write data, associated with the control information, is provided by a second output driver circuit to a second signal p... | 10/25/2011 |
| 7924048 | Memory controller that controls termination in a memory device A memory controller that controls termination in a memory device. The memory controller includes a data interface, command/address interface and termination control output. The data interface outputs write data onto a data line coupled to a data input of the memory ... | 04/12/2011 |
| 7782082 | Memory-module buffer with on-die termination In memory module having multiple data inputs to couple to signal lines of an external data path, multiple memory integrated-circuits (ICs) and a buffer IC, the buffer IC includes respective interfaces coupled to the data inputs and the memory ICs, a first terminatio... | 08/24/2010 |
| 7724590 | Memory controller with multiple delayed timing signals A memory controller with multiple delayed timing signals. Control information is provided by a first output driver circuit to a first signal path. Write data, associated with the control information, is provided by a second output driver circuit to a second signal p... | 05/25/2010 |
| 7675441 | Pilot-tone calibration for time-interleaved analog-to-digital converters A self-calibrating analog-to-digital converter (ADC). The ADC includes multiple component ADCs to generate respective digital representations of an input signal in response to respective timing signals that are offset in phase from one another, each component ADC ha... | 03/09/2010 |
| 7660183 | Low power memory device In a memory device having a memory core and a signal interface, receiving a command that specifies at least a portion of a memory access. During the memory access, transferring data between the memory core and the signaling interface, and transferring the data betwe... | 02/09/2010 |
| 7610544 | Erasure generation in a forward-error-correcting communication system A first data packet is received within an integrated circuit device and stored within a first memory thereof starting at a first address that is determined by the size of one or more previously received data packets. An error descriptor value is updated within a sec... | 10/27/2009 |
| 7602209 | Controlling memory devices that have on-die termination A memory controller for controlling integrated circuit memory devices that have on-die termination. The memory controller includes an output driver to output a first data signal onto a data line, and termination control circuitry to output termination control signal... | 10/13/2009 |
