Did You Know...
...that the inventor of the electric motor was a blacksmith named Thomas Davenport? Described as "a brilliantly unsuccessful inventor", Davenport invented the first rotary electric motor. In 1836 he headed out -- on foot -- from his Vermont home to file a patent application at the Patent Office in Washington, D.C. By the time he got there, he had squandered away his money and couldn't afford the $30 filing fee so he turned around and went home. When he later mailed in his application with money he'd raised, the Patent office was destroyed in a fire. He did finally get credit for his invention on Feb. 5, 1837.
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| Number | Title | Issue Date |
| 5110410 | Zinc sulfide planarization A procedure for planarizing a group II-VI composition which includes a resist and etch-back procedure wherein a thick resist coating relative to the degree of non-planarity is spun over a non-planar group II-VI layer to provide a planar resist surface. Th... | 05/05/1992 |
| 5111260 | Polysilicon FETs Field effect transistors in which the channel region is made of thin highly doped polysilicon which is preferably also hydrogen passivated.... | 05/05/1992 |
| 5109351 | Learning device and method Layered arrays of nearest-neighbor connected computation cells plus an error computation layer provide a learning network.... | 04/28/1992 |
| 5094973 | Trench pillar for wafer processing A T-shaped trench intersection shaped to make uniform the wall-to-wall spacing at the trench intersection and prevent the formation of voids when the trench is filled with a conformal insulating material.... | 03/10/1992 |
| 5091759 | Heterostructure field effect transistor A heterostructure field effect transistor having a buffer layer comprising a first compound semiconductor material. A layer of second semiconductor material different from the first material is formed over the buffer layer. The second layer has a total th... | 02/25/1992 |
| 5082522 | Method for forming patterned diamond thin films Preferred embodiments mask select regions of a circuit surface (141) prior to abrading the surface with diamond particles to form nucleation sites (200). The mask (150) is then removed prior to forming a diamond layer (160). Diamond layer (160) grows on t... | 01/21/1992 |
| 5081069 | Method for depositing a Tio2 layer using a periodic and simultaneous tilting and rotating platform motion Method and apparatus are disclosed for depositing a uniform layer of material, such as titanium dioxide, on the surface of an object, such as a silicon sphere of a solar array (7). Component gases are injected at predetermined rates into a heated reaction... | 01/14/1992 |
| 5079180 | Method of fabricating a raised source/drain transistor A raised source/drain transistor is provided having thin sidewall spacing insulators (54) adjacent the transistor gate (48). A first sidewall spacer (64) is disposed adjacent thin sidewall spacing insulator (54) and raised source/drain region (60). A seco... | 01/07/1992 |
| 5079192 | Method of preventing dislocation multiplication of bulk HgCdTe and LPE films during low temperature anneal in Hg vapor The disclosure relates to a method of forming samples of alloys of group II-VI compositions having minimum dislocations, comprising the steps of providing a sample of a group II-VI compound, providing an enclosed ampoule having the sample at one end porti... | 01/07/1992 |
| 5077231 | Method to integrate HBTs and FETs This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector laye... | 12/31/1991 |
| 5075241 | Method of forming a recessed contact bipolar transistor and field effect device Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, p... | 12/24/1991 |
| 5073519 | Method of fabricating a vertical FET device with low gate to drain overlap capacitance This is a vertical MOSFET device with low gate to drain overlap capacitance. It can comprise a semiconductor substrate 22 of the first conductivity type, a source region 24,26 of a second conductivity type formed in the upper surface of the substrate 22; ... | 12/17/1991 |
| 5072276 | Elevated CMOS A new class of CMOS integrated circuits, wherein the PMOS and NMOS devices are both configured as vertical transistors. One trench can contain a PMOS device, an NMOS device, and a gate which is coupled to control both the PMOS device and the NMOS device. ... | 12/10/1991 |
| 5068696 | Programmable interconnect or cell using silicided MOS transistors A programmable device (10) is formed from a silicided MOS transistor. The transistor (10) is formed at a face of a semiconductor layer (12), and includes a diffused drain region (17, 22) and a source region (19, 24) that are spaced apart by a channel regi... | 11/26/1991 |
| 5068756 | Integrated circuit composed of group III-V compound field effect and bipolar semiconductors Integrated circuits and fabrication methods incorporating both NPN (192, 194, 210) and PNP (196, 121, 124) heterojunction bipolar transistors together with N channel (198, 200, 216, 218) and P channel (202, 204, 220, 222) JFETs on a single substrate as il... | 11/26/1991 |
| 5068705 | Junction field effect transistor with bipolar device and method Vertical AlGaAs heterojunction bipolar transistors and GaAs junction field effect transistors are fabricated on a single gallium arsenide (GaAs) substrate to form an integrated circuit structure. The integration of these devices is made possible by a nove... | 11/26/1991 |
| 5065132 | Programmable resistor and an array of the same A programmable resistor 10 is provided having a resistive element 12. Resistive element 12 includes a substrate 26 formed by a layer of semiconductor of a first conductivity-type. A current path 32 is formed in substrate 26 by a layer of semiconductor of ... | 11/12/1991 |
| 5065208 | Integrated bipolar and CMOS transistor with titanium nitride interconnections A process is disclosed with integrated steps for fabricating bipolar and CMOS transistors. Mask, patterning and implanting steps are highly integrated to reduce the fabrication complexity. The integrated steps include a split level polysilicon step wherei... | 11/12/1991 |
| 5061653 | Trench isolation process The disclosure relates to the article and a method of forming a field oxide which extends over an isolation trench and the adjacent substrate wherein a portion of the trench insulating sidewall at the top region thereof is removed and replaced by polysili... | 10/29/1991 |
| 5059545 | Three terminal tunneling device and method A tunneling device (50) with the emitter (62) to collector (58) current transported by resonant tunneling through a quantum well (52) and controlled by carriers injected into the well (52) from a base (60) is disclosed. The injected carriers occupy a firs... | 10/22/1991 |
| 5057447 | Silicide/metal floating gate process The invention provides an integrated circuit capacitor with a silicided polysilicon electrode (which silicide has not been used as an etch stop) as a bottom plate and a metal layer as a top plate. Subsequent to the formation of a patterned polysilicon lay... | 10/15/1991 |
| 5053346 | Method for making a high speed gallium arsenide transistor Vertical buried emitter heterojunction bipolar transistors having greatly reduced emitter to base junction area and collector dimensions are fabricated in a gallium arsenide substrate to form an integrated circuit structure. The ability to scale these cri... | 10/01/1991 |
| 5049513 | Bi CMOS/SOI process flow The invention provides a bipolar transistor structure on a buried oxide layer for use in an integrated circuit and a method for fabricating the same. The invention may be incorporated into a method for fabricating bipolar transistors in a BiCMOS structure... | 09/17/1991 |
| 5047361 | NMOS transistor having inversion layer source/drain contacts A transistor (42) is provided having a gate conductor (44) formed adjacent a semiconductor substrate (46) and separated therefrom by a gate insulator (48). Sidewall spacers (52, 54) are formed at the sides of gate conductor (44) and adjacent semiconductor... | 09/10/1991 |
| 5047829 | Monolithic p-i-n diode limiter Monolithic gallium arsenide limiters (30) formed of p-i-n diodes (32, 34) that are distributed devices between conductors of coplanar waveguide sections (40, 42, 44) are disclosed. The diode doped regions underlie the coplanar conductors and the diode int... | 09/10/1991 |
| 5043293 | Dual oxide channel stop for semiconductor devices The disclosure relates to oxide-semiconductor interfaces which are grown with varying amounts of fixed positive (or negative) charge. The invention utilizes these different values to form a channel stop for a charge transfer device. For HgCdTe two differe... | 08/27/1991 |
| 5036376 | Passivation oxide conversion A method of passivation of Hg1-x Cdx Te and similar semiconductors by surface oxidation (such as anodic) followed by chemical conversion of the oxide to either sulfide or selenide or a combination of both is disclosed. Preferred embo... | 07/30/1991 |
| 5028296 | Annealing method A three step annealing treatment for Hg1-x Cdx Te includes a high temperature anneal to reduce excess tellurium, followed by an intermediate temperature anneal to reduce the supersaturation of metal vacancies, and lastly a low temper... | 07/02/1991 |
| 5028879 | Compensation of the gate loading loss for travelling wave power amplifiers The disclosure relates to a circuit to reduce the gate loss in a semiconductor travelling wave power amplifier using series capacitors on the gate feeding lines for a distributed amplifier design. The circuit arrangement significantly increases the gate w... | 07/02/1991 |
| 5021662 | Method and apparatus for real-time in-line material monitoring An apparatus (10) for real-time in-line monitoring of a material (26) comprises a blackbody source (12), a first set of reflective surfaces (17) and a second set of reflective surfaces (38). Electromagnetic radiation (16) is emitted from the blackbody sou... | 06/04/1991 |
| 5019525 | Method for forming a horizontal self-aligned transistor A method for forming a self-aligned horizontal transistor includes the step of first defining a narrow base contact on an isolated N-tank (10) to define a first reference edge (41). A layer of sidewall oxide (40) is then disposed on the vertical wall of t... | 05/28/1991 |
| 5012619 | Method and apparatus for forming spheres A method and apparatus for forming silicon spheres (40) from irregular-shaped particles (38) for use in solar cells are disclosed. The apparatus (10) generally comprises a vertically aligned cylindrical chamber (12) having an abrasive lining (32) integral... | 05/07/1991 |
| 5013682 | Method for selective epitaxy using a WSI mask Selective growth of GaAs and related semiconductors (34) by use of tungsten silicide and related materials for growth masks (36) plus devices incorporating the selective growth plus use of the growth masks as electrical contacts are disclosed. The deposit... | 05/07/1991 |
| 5010032 | Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects A process for making CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat. A titanium nitride ... | 04/23/1991 |
| 5010386 | Insulator separated vertical CMOS A complementary semiconductor structure comprises a substrate of a first conductivity type upon which a first channel layer of a second conductivity type is formed. The first source/drain layer of the first conductivity type is formed on the surface of th... | 04/23/1991 |
| 4956689 | High speed gallium arsenide transistor and method Vertical buried emitter heterojunction bipolar transistors having greatly reduced emitter to base junction area and collector dimensions are fabricated in a gallium arsenide substrate to form an integrated circuit structure. The ability to scale these cri... | 09/11/1990 |
