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| Number | Title | Issue Date |
| 6566687 | Metal induced self-aligned crystallization of Si layer for TFT The present invention discloses a semiconductor device, a thin film transistor (TFT), and a process for forming a TFT. The semiconductor device according to the present invention comprises a top-gate type thin film transistor (TFT), said top-gate type TFT... | 05/20/2003 |
| 6552339 | Micro goniometer for scanning probe microscopy A goniometer for performing scanning probe microscopy on a substrate surface is disclosed. The goniometer has a cantilever, having a cantilevered end and a supported end and a tip disposed at the cantilevered end of the cantilever. The goniometer also has... | 04/22/2003 |
| 6541356 | Ultimate SIMOX A method of forming a silicon-on-insulator (SOI) substrate having a buried oxide region that has a greater content of thermally grown oxide as compared to oxide formed by implanted oxygen ions is provided. Specifically, the inventive SOI substrate is form... | 04/01/2003 |
| 6541398 | Ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device containing the same A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing plasma enhanced chemical vapor deposition ("PECVD") process is disclosed. Electro... | 04/01/2003 |
| 6525427 | BEOL decoupling capacitor An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefor... | 02/25/2003 |
| 6525341 | Thin film transistor, liquid crystal display device and method of fabricating the thin film transistor The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a ... | 02/25/2003 |
| 6515335 | Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov... | 02/04/2003 |
| 6511876 | High mobility FETS using A1203 as a gate oxide A method of forming a high-k dielectric material which exhibits a substantially lower amount of trap charge within a gate stack region is provided. The method maintains high-temperatures (250° C. or above) such that the substrate wafer is not cooled duri... | 01/28/2003 |
| 6512683 | System and method for increasing the speed of memories The speed of memories is increased by trading memory density (or area) for speed (or cycle time). An n by n memory array is used to reduce the memory cycle time by 1/n. For example, if an existing memory cycle time is 6 ns, in order to achieve a 3ns (or n... | 01/28/2003 |
| 6504777 | Enhanced bitline equalization for hierarchical bitline architecture In a high density dynamic memory circuit, the sense amplifiers are shared by several bitlines in order to maintain a high density and low power design. However, the bitline equalization level drifts after several cycles of operation, caused by an unbalanc... | 01/07/2003 |
| 6495429 | Controlling internal thermal oxidation and eliminating deep divots in SIMOX by chlorine-based annealing A method to control the quality of a buried oxide region, and to substantially reduce or eliminate deep divots in SOI substrates is provided. Specifically, the inventive method includes the steps of implanting oxygen ions into a surface of a Si-containing... | 12/17/2002 |
| 6492708 | Integrated coil inductors for IC devices A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL me... | 12/10/2002 |
| 6475072 | Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP) A method and apparatus is described incorporating a semiconductor substrate, a CMP tool, a brush cleaning tool, and a chemical wafer cleaning tool. The CMP is performed with a down force of 1 psi, a backside air pressure of 0.5 psi, a platen speed of 50 r... | 11/05/2002 |
| 6441491 | Ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device containing the same A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing plasma enhanced chemical vapor deposition ("PECVD") process is disclosed. Electro... | 08/27/2002 |
| 6434076 | Refresh control circuit for low-power SRAM applications A power management circuit for an SRAM system including one or more isolated memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to local supplies during an ... | 08/13/2002 |
| 6426905 | High speed DRAM local bit line sense amplifier Disclosed is a high speed sense amplifier circuit designed for sensing data in one-transistor DRAM memory cells on bit lines within DRAM macros. The circuit utilizes a charge transfer scheme to rapidly remove charge from a small sensing first capacitor C1... | 07/30/2002 |
| 6400619 | Micro-cell redundancy scheme for high performance eDRAM A new micro-cell redundancy scheme for a wide bandwidth embedded DRAM having a SRAM cache interface. For each bank of micro-cell array units comprising the eDRAM, at least one micro-cell unit is prepared as the redundancy to replace a defected micro-cell ... | 06/04/2002 |
| 6349067 | System and method for preventing noise cross contamination between embedded DRAM and system chip A complete solution to block noise from eDRAM macro to the analog core, and vice verse, in a system-on-chip IC design. Specifically, there is provided a first isolated triple well structure formed in the IC for reducing noise component resulting from oper... | 02/19/2002 |
| 6346484 | Method for selective extraction of sacrificial place-holding material used in fabrication of air gap-containing interconnect structures The present invention relates to formation of air gaps in metal/insulator interconnect structures, and to the use of supercritical fluid (SCF)-based methods to extract sacrificial place-holding materials to form air gaps in a structure. Supercritical flui... | 02/12/2002 |
| 6331486 | Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy A method of reducing contact resistance of metal silicides to a silicon-containing substrate is provided. The method includes first forming a metal germanium layer over a silicon-containing substrate. An optionally oxygen barrier layer may be formed over ... | 12/18/2001 |
| 6259137 | Defect induced buried oxide (DIBOX) for throughput SOI A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing a first low energy implantation step to create a stable defect region; a second low energy implantation step to create an amorphous layer adjacent ... | 07/10/2001 |
| 6236589 | Ultra high density storage media and method thereof A storage media for storing information having a substrate. The substrate has an upper surface and a molecular weight greater than 5,000. Preferably the material is a polymer. The material has a plurality of piles of molecular chains in selected areas for... | 05/22/2001 |
| 6203613 | Atomic layer deposition with nitrate containing precursors Metal nitrate-containing precursor compounds are employed in atomic layer deposition processes to form metal-containing films, e.g. metal, metal oxide, and metal nitride, which films exhibit an atomically abrupt interface and an excellent uniformity.... | 03/20/2001 |
| 6202191 | Electromigration resistant power distribution network Method for forming a novel power grid structure for integrated circuit semiconductor chip devices that exhibits increased electromigration resistance by including diffusion blocking interlevel contacts and employing a regular array of conducting line elem... | 03/13/2001 |
| 6197222 | Lead free conductive composites for electrical interconnections An electrically conductive paste which includes a thermoplastic polymer, a conductive metal powder and an organic solvent system is disclosed. The invention further encompasses an electrically conductive composite which includes the aforementioned thermop... | 03/06/2001 |
| 6172385 | Multilayer ferroelectric capacitor structure Multilayer ferroelectric capacitor structures comprising a ferroelectric film having a combination of different ferroelectric materials or compositions such as strontium bismuth tantalate, strontium bismuth niobate, bismuth titanate, strontium bismuth tan... | 01/09/2001 |
| 6130472 | Moisture and ion barrier for protection of devices and interconnect structures The present invention provides polymeric materials that can be used as a moisture/ion barrier layer for inhibiting the penetration of moisture and/or ions for coming into contact with the metal wiring found in chip level interconnects. The present inventi... | 10/10/2000 |
| 6114937 | Integrated circuit spiral inductor High quality factor (Q) spiral and toroidal inductor and transformer are disclosed that are compatible with silicon very large scale integration (VLSI) processing, consume a small IC area, and operate at high frequencies. The spiral inductor has a spiral ... | 09/05/2000 |
| 6100523 | Micro goniometer for scanning microscopy A goniometer for performing scanning probe microscopy on a substrate surface is disclosed. The goniometer has a cantilever, having a cantilevered end and a supported end and a tip disposed at the cantilevered end of the cantilever. The goniometer also has... | 08/08/2000 |
| 6091122 | Fabrication of mid-cap metal gates compatible with ultra-thin dielectrics A method of fabricating a mid-gap workfunction tungsten gate or W electrode directly onto a gate dielectric material for use in high speed/high density advanced MOS and CMOS devices is provided which utilizes low temperature/low pressure CVD of a tungsten... | 07/18/2000 |
| 6087242 | Method to improve commercial bonded SOI material A method of improving the bonding characteristics of a previously bonded silicon on insulator (SOI) structure is provided. The improvement in the bonding characteristics is achieved in the present invention by, optionally, forming an oxide cap layer on th... | 07/11/2000 |
| 6054329 | Method of forming an integrated circuit spiral inductor with ferromagnetic liner High quality factor (Q) spiral and toroidal inductor and transformer are disclosed that are compatible with silicon very large scale integration (VLSI) processing, consume a small IC area, and operate at high frequencies. The spiral inductor has a spiral ... | 04/25/2000 |
| 6017618 | Ultra high density storage media and method thereof A storage media for storing information having a substrate. The substrate has an upper surface and a molecular weight greater than 5,000. Preferably the material is a polymer. The material has a plurality of piles of molecular chains in selected areas for... | 01/25/2000 |
| 5998250 | Compound electrode stack capacitor This invention is directed to a semiconductor memory device including a storage element comprising a ferroelectric material or a capacitor dielectric material between a top (plate) electrode and a bottom (stack) electrode. In particular, the invention per... | 12/07/1999 |
