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| Number | Title | Issue Date |
| 6440639 | High-aspect ratio resist development using safe-solvent mixtures of alcohol and water A high-aspect ratio resist profile is obtained using a development process wherein a mixture of an alcohol and water is used as the developer. The alcohol/water mixture is non-toxic, and does not cause excess swelling and cracking of the resist during the... | 08/27/2002 |
| 6440808 | Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-poly A sub-0.1 μm MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and sili... | 08/27/2002 |
| 6429061 | Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation A strained Si CMOS structure is formed by steps which include forming a relaxed SiGe layer on a surface of a substrate; forming isolation regions and well implant regions in said relaxed SiGe layer; and forming a strained Si layer on said relaxed SiGe lay... | 08/06/2002 |
| 6093947 | Recessed-gate MOSFET with out-diffused source/drain extension The present invention relates to a recessed channel/gate MOSFET structure which comprises a semiconductor wafer having a plurality of shallow trench isolation regions embedded therein, wherein between each adjacent shallow trench isolation region is a fie... | 07/25/2000 |
| 6013548 | Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array A densely packed array of vertical semiconductor devices, having pillars and deep trench capacitors, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped... | 01/11/2000 |
| 5998292 | Method for making three dimensional circuit integration The present invention relates to a method for interconnecting, through high-density micro-post wiring, multiple semiconductor wafers with lengths of about a millimeter or below. Specifically, the method of the present invention comprises etching at least ... | 12/07/1999 |
| 5929477 | Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower do... | 07/27/1999 |
| 5920086 | Light emitting device A device for generating radiant energy comprising a first electrode, a second electrode spaced apart from said first electrode, a material disposed between and in electrical communication with first and second electrodes, which emits radiant energy upon a... | 07/06/1999 |
| 5874760 | 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation A densely packed array of vertical semiconductor devices and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the... | 02/23/1999 |
