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...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
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| Number | Title | Issue Date |
| 6591277 | Dynamic object persistence Methods and apparatus for persisting objects to a database are disclosed. A set of meta-level objects (120) are defined, each object also having defined a persistence strategy. Each object also has a set of attributes which have their own respective persi... | 07/08/2003 |
| 6537886 | Ultra-shallow semiconductor junction formation A method for fabricating an ultra-shallow semiconductor junction using a high energy co-implantation step; a low energy dopant implantation step, and a fast isothermal annealing step is provided. Microelectronics devices such as FET and CMOS devices conta... | 03/25/2003 |
| 6519765 | Method and apparatus for eliminating redundant array range checks in a compiler Java language is, as its specification, capable of detecting an access exceeding an array range, and when there is no user-defined exception handler, moving control to an invoked method after getting out of a method in which an exception occurred, or when... | 02/11/2003 |
| 6516460 | Debugging multiple related processes simultaneously Methods, systems and articles of manufacture comprising a computer usable medium having computer readable program code means therein are provided for debugging multiple related processes simultaneously and more particularly provided for debugging multiple... | 02/04/2003 |
| 6504173 | Dual gate FET and process The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench is... | 01/07/2003 |
| 6470494 | Class loader This invention relates to the loading of classes in programming environments, and in particular, Java programming environments. This invention discloses a system and method that permits dynamic loading of classes during the execution of Java programs. Thi... | 10/22/2002 |
| 6453380 | Address mapping for configurable memory system In a system in which data are stored in an interleaved fashion in a memory consisting of a plurality of memory banks, a method and means are provided for mapping a given address into a memory bank and an internal memory bank address. Lookup table means (L... | 09/17/2002 |
| 6427154 | Method of delaying space allocation for parallel copying garbage collection The present invention relates to a method of delaying space allocation for parallel copying garbage collection in a data processing system comprising a memory divided in a current area (from-space) used by at least a program thread during current program ... | 07/30/2002 |
| 6426012 | Wet chemical etch process for patterning MRAM magnetic layers A three-part etching process is employed to selectively pattern exposed magnetic film layers of a magnetic thin film structure. The magnetic structure to be etched includes at least one bottom magnetic film layer and at least one top film layer which are ... | 07/30/2002 |
| 6077745 | Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower do... | 06/20/2000 |
| 6034389 | Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array A densely packed array of vertical semiconductor devices, having pillars and deep trench capacitors, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped... | 03/07/2000 |
| 6033957 | 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation A densely packed array of vertical semiconductor devices and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the... | 03/07/2000 |
