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| Number | Title | Issue Date |
| 6606533 | Method and arrangement for controlling image size of integrated circuits on wafers through post-exposure bake hotplate-specific dose feedback A method and an arrangement for the processing of wafers on post-exposure bake hotplates along multiple processing paths, each of which may result in different integrated circuit images, and adjust the exposure dose based on the path through the process, ... | 08/12/2003 |
| 6570209 | Merged self-aligned source and ONO capacitor for split gate non-volatile memory A non-volatile memory cell having a oxide-nitride-oxide (ONO) capacitor merged with a polysilicon strap diffusion region is obtained by forming a film stack on a surface of a substrate, said film stack comprising at least a floating gate oxide layer, a fl... | 05/27/2003 |
| 6557163 | Method of photolithographic critical dimension control by using reticle measurements in a control algorithm A method of implementing a new reticle for manufacturing semiconductors on a wafer which involves performing measurements on the reticle and assigning an initial exposure dose by using a predetermined algorithm. The exposure control system utilizes reticl... | 04/29/2003 |
| 6555859 | Flip FERAM cell and method to form same A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a... | 04/29/2003 |
| 6548345 | Method of fabricating trench for SOI merged logic DRAM Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods... | 04/15/2003 |
| 6534371 | C implants for improved SiGe bipolar yield A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, th... | 03/18/2003 |
| 6528821 | Optimized reachthrough implant for simultaneously forming an MOS capacitor A method of forming a diffusion region in a silicon substrate having low-resistance, acceptable defect density, reliability and process control comprising the steps of: (a) subjecting a silicon substrate to a first ion implantation step, said first ion im... | 03/04/2003 |
| 6521506 | Varactors for CMOS and BiCMOS technologies Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a sub... | 02/18/2003 |
| 6511873 | High-dielectric constant insulators for FEOL capacitors Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the cap... | 01/28/2003 |
| 6507063 | Poly-poly/MOS capacitor having a gate encapsulating first electrode layer A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said r... | 01/14/2003 |
| 6387596 | Method of forming resist images by periodic pattern removal The present invention provides a method of forming nested and isolated images in a photosensitive resist. In the disclosed method, the entire surface of the photosensitive resist or selected regions thereof is exposed to a first mask having a set of neste... | 05/14/2002 |
| 6333202 | Flip FERAM cell and method to form same A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a... | 12/25/2001 |
| 6258661 | Formation of out-diffused bitline by laser anneal The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused ... | 07/10/2001 |
| 6258490 | Transmission control mask utilized to reduce foreshortening effects A transmission controlled mask (TCM) for providing effective and accurate printing of images on a semiconductor wafer is defined. The transmission controlled mask (TCM) of the present invention includes opaque regions, clear regions, and transmission cont... | 07/10/2001 |
| 6235439 | Method for controlling image size of integrated circuits on wafers supported on hot plates during post exposure baking of the wafers A method for the control of wafer surface temperatures during post exposure bake on hot plates of wafers which carry integrated circuits. Also disclosed is a method of maximizing image size uniformity for integrated circuits through the zonal control of t... | 05/22/2001 |
| 6232170 | Method of fabricating trench for SOI merged logic DRAM Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods... | 05/15/2001 |
| 6221680 | Patterned recess formation using acid diffusion The present invention relates to a method for providing patterned recess formation in a previously recessed area of a semiconductor structure, i.e. DRAM trench capacitor, using acid diffusion to selectively activate some, but not all of the acid sensitive... | 04/24/2001 |
| 6218315 | HTO (high temperature oxide) deposition for capacitor dielectrics Reliable HTO (High Temperature Oxide) dielectrics are provide by a rapid thermal chemical vapor deposition (RTCVD) process in which a low pressure and a high ratio of reactants, e.g., oxygen-containing gas to silane-containing gas, is employed. Specifical... | 04/17/2001 |
| 6215125 | Method to operate GEF4 gas in hot cathode discharge ion sources The present invention provides a method of extending, i.e. prolonging, the operating lifetime of hot cathode discharge ion source by utilizing and introducing a nitrogen-containing co-bleed gas into an ion implantation apparatus which contains at least a ... | 04/10/2001 |
| 6214494 | Serif mask design methodology based on enhancing high spatial frequency contribution for improved printability A proximity correction serif design methodology is described that provides improved inner and outer corner rounding, line end shortening, as well as improvements in more general undesirable two-dimensional shape distortions introduced into the lithographi... | 04/10/2001 |
| 6207493 | Formation of out-diffused bitline by laser anneal The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused ... | 03/27/2001 |
| 6127071 | Serif mask design for correcting severe corner rounding and line end shortening in lithography A photolithographic mask for conducting illumination from a light source onto a semiconductor surface during a microlithographic manufacturing process. The mask includes a line end portion of a width w and including two corners, each corner defining a res... | 10/03/2000 |
| 6100506 | Hot plate with in situ surface temperature adjustment An arrangement and method for controlling individual zones of a hot plate which is employed in a post exposure bake step of wafers in the fabrication of semi-conductor devices incorporating photolithographic processes using chemically amplified resist sys... | 08/08/2000 |
| 6015745 | Method for semiconductor fabrication An SOI semiconductor design methodology enables the implementation of simplified STI processes by the design and formation of a shallow trench isolation frame around an electrically active semiconductor region. The simplified STI processes include the fab... | 01/18/2000 |
