Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 7170317 | Sum bit generation circuit Sum bit generation circuit includes first logic generating first signal as XOR of first and second input signals and second signal as the inverse of XOR of the first and second input signals; second logic receiving the first and second signals generated by first log... | 01/30/2007 |
| 7136888 | Parallel counter and a logic circuit for performing multiplication A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of co... | 11/14/2006 |
| 7120837 | System and method for delayed error handling A system and method for delayed error handling. In one embodiment, a computerized method includes sending a Small Computer Systems Interface (SCSI) command to a peripheral device through a network connection, waiting for a SCSI response from the peripheral device, d... | 10/10/2006 |
| 7098216 | Thiazolopyrimidines useful as TNFα inhibitors The invention provides derivatives of thiazolo[4,5-d1]pyrimidine and their use as inhibitors of proinflammatory cytokines. ... | 08/29/2006 |
| 6946413 | Composite material with cloth-like feel The present invention provides a wet-wipe comprising a non-woven composite elastic material comprising a non-woven elastic layer; and a non-woven gatherable layer. The gatherable layer is bonded to the elastic layer at at least two points; and is gathered between th... | 09/20/2005 |
| 6237021 | Method and apparatus for the efficient processing of data-intensive applications A system and method for providing a sustained, peak performance computing architecture is provided. A hardware processing architecture is provided for performing repeated algorithm iterations, wherein each of the algorithm iterations is performed on a par... | 05/22/2001 |
| 6081528 | Shared buffer memory architecture for asynchronous transfer mode switching and multiplexing technology An ATM switch including a multi-port memory is described. The multi-port memory having a dynamic random access memory (DRAM) and a plurality of input and output serial access memories (SAMs). Efficient, flexible transfer circuits and methods are described... | 06/27/2000 |
| 6074659 | Therapeutic inhibitor of vascular smooth muscle cells Methods are provided for inhibiting stenosis following vascular trauma or disease in a mammalian host, comprising administering to the host a therapeutically effective dosage of a therapeutic conjugate containing a vascular smooth muscle binding protein t... | 06/13/2000 |
| 6058058 | Memory device with a sense amplifier A circuit for a sense amplifier (14) for use with a memory device (10). The circuit includes two devices (40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second devic... | 05/02/2000 |
| 6052303 | Apparatus and method for selecting data bits read from a multistate memory An apparatus and method which sequentially selects subsets of data bits read in parallel from an array of memory cells (each cell being operated as a multistate memory device) and sequentially asserts the selected subsets to a data bus. Preferably, the ce... | 04/18/2000 |
| 6034906 | High and negative voltage compare A voltage of a relatively large potential internal signal in an integrated circuit is tested by providing a comparison signal having a voltage that is lower than the voltage of the relatively large potential internal signal. The voltage of the relatively ... | 03/07/2000 |
| 6030408 | Acupressure treatment device The present invention discloses an acupressure device for use on a selected skin surface portion of a human body. The device comprises a thin flexible base sheet having a first side, a second side and a margin. The margin has at least a portion of its len... | 02/29/2000 |
| 6031263 | DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate A floating gate transistor has a reduced barrier energy at an interface between a gallium nitride (GaN) or gallium aluminum nitride (GaAlN) floating gate an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltag... | 02/29/2000 |
| 6027990 | Using implants to lower anneal temperatures A method for lowering the anneal temperature required to form a multi-component material, such as refractory metal silicide. A shallow layer of titanium is implanted in the bottom of the contact area after the contact area is defined. Titanium is then dep... | 02/22/2000 |
| 6018236 | Differential voltage regulator A voltage regulator (10) that regulates an input voltage. The voltage regulator (10) includes a current source (20) that generates a reference current. The voltage regulator also includes a voltage translation circuit (30), coupled to and responsive to th... | 01/25/2000 |
| 6015997 | Semiconductor structure having a doped conductive layer Methods and apparatus for forming word line stacks comprise one, or a combination of the following: a silicon diffusion barrier layer, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer; an amorphous silicon diffus... | 01/18/2000 |
| 6016561 | Output data compression scheme for use in testing IC memories A memory system operable in a normal mode of operation and a test mode of operation includes sensing circuitry which generates x number of data bits during a read cycle. A read path circuit, coupled to the sensing circuitry, transfers the x number of data... | 01/18/2000 |
| 6014332 | Flash memory with adjustable write operation timing A flash memory is described which includes circuitry to determine how many memory cells can be programmed in a single write operation by measuring the power available for programming. The available power is determined by monitoring Vcc and/or Vpp prior to... | 01/11/2000 |
| 6009029 | Circuit and method for antifuse stress test A test circuit for stress testing antifuses before programming. The test circuit provides a voltage to an antifuse detection circuit during antifuse stress testing. In one embodiment, the provided voltage is externally received at a probe pad. In another ... | 12/28/1999 |
| 6009249 | Automated load determination for partitioned simulation A method and device for automatically generating load circuits for a netlist. A computer system having a schematic for a circuit is used to create a netlist. While constructing the netlist, instances are checked for directives. The directives indicate tha... | 12/28/1999 |
| 6008970 | Power supply clamp circuitry for electrostatic discharge (ESD) protection Circuitry is provided which increases the efficiency of electrostatic discharge (ESD) power supply clamping circuitry to sink larger currents during an ESD event on a power supply node. Voltage clamp circuits capable of providing ESD protection to a suppl... | 12/28/1999 |
| 6009025 | Partial replacement of partially defective memory devices The partial replacement of partially defective integrated circuit devices, such as memory devices, is disclosed. In one embodiment, the data lines coupled to different sections of the memory array of a memory device have inserted in series therein normall... | 12/28/1999 |
| 6004838 | ESD protection using selective siliciding techniques The present invention relates to methods and apparatus for manufacturing semiconductor devices, and in particular for forming electrostatic discharge (ESD) protection devices, using selective siliciding, in a CMOS integrated circuit. Predetermined dischar... | 12/21/1999 |
| 6004825 | Method for making three dimensional ferroelectric memory A three dimensional ferroelectric memory device formed on a semiconductor substrate has insulative material formed between rows of conductors to reduce cross talk between the conductors. Access circuitry or other circuitry is formed beneath the three dime... | 12/21/1999 |
| 6002613 | Data communication for memory A memory circuit is described which includes memory cells for storing data. The memory circuit can be read from or written to by an external system such as a microprocessor or core logic chip set. The microprocessor provides memory cell address data to th... | 12/14/1999 |
| 5996106 | Multi bank test mode for memory devices A multiple bank memory device is described which can be tested by accessing the multiple memory banks simultaneously. The memory includes a test mode trigger which initiates a test which writes and reads from memory cells located in different memory banks... | 11/30/1999 |
| 5995982 | Method and device for file transfer by cascade release A method and apparatus for transferring data files to several computers on a network is disclosed. The cascade release maintains a list of computers to which the file is to be distributed. This list is subdivided and only the first computers on the lists ... | 11/30/1999 |
| 5994777 | Method and support structure for air bridge wiring of an integrated circuit A process of manufacturing integrated circuits is disclosed for designing and implementing a hierarchical wiring system. The interconnection requirements are sorted and designed into a particular wiring level according to length. Support structures may be... | 11/30/1999 |
| 5995423 | Method and apparatus for limiting bitline current A flash memory integrated circuit includes wordlines, bitlines, an array of floating gate transistor memory cells, and current limiters. Each floating transistor memory cell is coupled to one of the bitlines and one of the wordlines. The current limiters ... | 11/30/1999 |
| 5990538 | High resistivity integrated circuit resistor The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created durin... | 11/23/1999 |
| 5989958 | Flash memory with microcrystalline silicon carbide film floating gate A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductiv... | 11/23/1999 |
| 5982697 | Method for initializing and reprogramming a control operation feature of a memory device A method for initially programming a synchronous dynamic random access memory (SDRAM) device to have a first control operating option in response to a first command and for reprogramming the SDRAM device to have a second control operating option in respon... | 11/09/1999 |
| 5976930 | Method for forming gate segments for an integrated circuit A method for forming gate segments in an integrated circuit. The method begins by forming a shallow trench isolation region outwardly from a layer of semiconductor material to isolate a plurality of active regions of the integrated circuit. After the isol... | 11/02/1999 |
| 5978311 | Memory with combined synchronous burst and bus efficient functionality A memory device is described which is operable in both a synchronous mode and a bus efficient mode (BE). Address and data register circuitry provide multiple propagation paths which can be selected based upon the operating mode and function performed. The... | 11/02/1999 |
| 5978309 | Selectively enabled memory array access signals A synchronous memory device is described which uses unique column select circuitry. The memory device pipelines address decode and column select operation to increase clock frequency. The column select circuitry includes latches and coupling circuits. The... | 11/02/1999 |
| 5977763 | Circuit and method for measuring and forcing an internal voltage of an integrated circuit A circuit (10) for reading a voltage at a voltage source (14) of an integrated circuit (12). In one version, the circuit (110) involves a pass circuit (118) that has an input coupled to the node (114) of the integrated circuit (12). The circuit (110) prov... | 11/02/1999 |
| 5973974 | Regressive drive sense amplifier A pull-down circuit in a sense amplifier, such a sense amplifier in a memory integrated circuit, includes a pull-down transistor having a drain coupled to a common node, a gate, and a source coupled to ground. An inverter provides a gate control signal to... | 10/26/1999 |
| 5970008 | Efficient method for obtaining usable parts from a partially good memory integrated circuit An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the inte... | 10/19/1999 |
| 5962174 | Multilayer reflective mask The present invention is a multi layer reflective mask, and a method of fabricating the same, wherein the mask comprises a planar substrate, and a plurality of polished optically reflective regions fabricated on the substrate in an alternating pattern suc... | 10/05/1999 |
| 5959897 | System and method for writing data to memory cells so as to enable faster reads of the data using dual wordline drivers A memory system including an array of memory cells (e.g., flash memory cells) connected along wordlines and bitlines, two physically separated sets of wordline drivers (each for driving a different subset of the wordlines), and circuitry for writing data ... | 09/28/1999 |
