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Felix Hoffmann, a German chemist, was searching for something to relieve his father's arthritis. In doing so, he "rediscovered" acetylsalicylic acid and in 1900, patented a stable process for developing it. Hence, we have aspirin.
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| Number | Title | Issue Date |
| 8159031 | SOI substrates and SOI devices, and methods for forming the same An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any... | 04/17/2012 |
| 8159015 | Method and structure for forming capacitors and memory devices on semiconductor-on-insulator (SOI) substrates A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitor... | 04/17/2012 |
| 8141025 | Method of performing timing analysis on integrated circuit chips with consideration of process variations A method for verifying whether a circuit meets timing constraints by performing an incremental static timing analysis in which slack is represented by a distribution that includes sensitivities to various process variables. The slack at an endpoint is computed by pr... | 03/20/2012 |
| 8138604 | Metal cap with ultra-low k dielectric material for circuit interconnect applications An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of abo... | 03/20/2012 |
| 8138068 | Method to form nanopore array A method of forming nanopore is provided that includes forming a first structure on a substrate, and forming a second structure overlying the first structure. An intersecting portion of the first and the second structures is etched to provide an opening of nanopore ... | 03/20/2012 |
| 8138029 | Structure and method having asymmetrical junction or reverse halo profile for semiconductor on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region... | 03/20/2012 |
| 8132134 | Closed-loop 1×N VLSI design system Embodiments that design integrated circuits using a closed loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may com... | 03/06/2012 |
| 8129269 | Method of improving mechanical properties of semiconductor interconnects with nanoparticles In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the propertie... | 03/06/2012 |
| 8129234 | Method of forming bipolar transistor integrated with metal gate CMOS devices A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor s... | 03/06/2012 |
| 8122411 | Method of performing static timing analysis considering abstracted cell's interconnect parasitics An abstraction model supporting multiple hierarchical levels is inputted into a generalized static timing analysis of a hierarchical IC chip design to analyze and optimize the design of circuits integral to the chip containing a plurality of macro abstracts. An elec... | 02/21/2012 |
| 8122404 | Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a stat... | 02/21/2012 |
| 8120179 | Air gap interconnect structures and methods for forming the same A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the die... | 02/21/2012 |
| 8120058 | High-drive current MOSFET A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity an... | 02/21/2012 |
| 8115575 | Active inductor for ASIC application An apparatus and method for manufacturing low-cost high-density compact active inductor module using existing DRAM, SRAM and logic process integration. The elements of the active inductor modules are formed by three semiconductor devices including nMOS devices, deep... | 02/14/2012 |
| 8115254 | Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI... | 02/14/2012 |
| 8110465 | Field effect transistor having an asymmetric gate electrode The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises... | 02/07/2012 |
| 8108815 | Order independent method of performing statistical N-way maximum/minimum operation for non-Gaussian and non-linear distributions A method and system to improve the performance of an integrated circuit (IC) chip by removing timing violations detected by performing a statistical timing analysis, given distributions of process and environmental sources of variation. The distributions are quantiz... | 01/31/2012 |
| 8103997 | Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the prim... | 01/24/2012 |
| 8093644 | Multiwalled carbon nanotube memory device A carbon nanotube based memory device comprises a set of three concentric carbon nanotubes having different diameters. The diameters of the three concentric carbon nanotubes are selected such that an inner carbon nanotube is semiconducting, and intershell electron t... | 01/10/2012 |
| 8088663 | SRAM cell having a rectangular combined active area planar pass gate and planar pull-down NFETS A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a diffe... | 01/03/2012 |
| 8076734 | Semiconductor structure including self-aligned deposited gate dielectric A semiconductor structure, such as a field effect device structure, and more particularly a CMOS structure, includes a gate dielectric that is at least in-part aligned to an active region of a semiconductor substrate over which is located the gate dielectric. The ga... | 12/13/2011 |
| 8062951 | Method to increase effective MOSFET width An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a crystal orientation. A... | 11/22/2011 |
| 8056038 | Method for efficiently checkpointing and restarting static timing analysis of an integrated circuit chip A method for loading checkpoint timing in an environment where the boundary arrival times, slews, required arrival times, or loads differ from the checkpoint run. A timing checkpoint file generated for one or more hierarchical modules, during which each input is ass... | 11/08/2011 |
| 8053823 | Simplified buried plate structure and process for semiconductor-on-insulator chip A structure is provided herein which includes an array of trench capacitors having at least portions disposed below a buried oxide layer of an SOI substrate. Each trench capacitor shares a common unitary buried capacitor plate which includes at least a portion of a ... | 11/08/2011 |
| 8042070 | Methods and system for analysis and management of parametric yield Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off... | 10/18/2011 |
| 8037441 | Gridded-router based wiring on a non-gridded library A computerized method for automatically generating a grid-based derivative of a non-gridded cell library of an integrated circuit design comprises the step of determining at least one valid position of at least one wiring element of a circuit of the first cell libra... | 10/11/2011 |
| 8037433 | System and methodology for determining layout-dependent effects in ULSI simulation A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal a... | 10/11/2011 |
| 8035141 | Bi-layer nFET embedded stressor element and integration to enhance drive current A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first l... | 10/11/2011 |
| 8022488 | High-performance FETs with embedded stressors A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a ... | 09/20/2011 |
| 8013324 | Structurally stabilized semiconductor nanowire In one embodiment, a semiconductor nanowire having a monotonically increasing width with distance from a middle portion toward adjoining semiconductor pads is provided. A semiconductor link portion having tapered end portions is lithographically patterned. During th... | 09/06/2011 |
| 8004060 | Metal gate compatible electrical antifuse A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurren... | 08/23/2011 |
| 8003488 | Shallow trench isolation structure compatible with SOI embedded DRAM A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of t... | 08/23/2011 |
| 7999332 | Asymmetric semiconductor devices and method of fabricating A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the... | 08/16/2011 |
| 7996812 | Method of minimizing early-mode violations causing minimum impact to a chip design A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode v... | 08/09/2011 |
| 7989233 | Semiconductor nanowire with built-in stress A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a g... | 08/02/2011 |
| 7987440 | Method and system for efficient validation of clock skews during hierarchical static timing analysis A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arriva... | 07/26/2011 |
| 7977712 | Asymmetric source and drain field effect structure A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor s... | 07/12/2011 |
| 7977032 | Method to create region specific exposure in a layer A method of selectively altering material properties of a substrate in one region while making a different alteration of material properties in an adjoining region is provided. The method includes selectively masking a first portion of the substrate during a first e... | 07/12/2011 |
| 7968975 | Metal wiring structure for integration with through substrate vias An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-... | 06/28/2011 |
| 7960223 | Structure and method to integrate dual silicide with dual stress liner to improve CMOS performance The present invention provides a semiconducting device including a substrate including a semiconducting surface having an n-type device in a first device region and a p-type device in a second device region, the n-type device including a first gate structure present... | 06/14/2011 |
