Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 6589376 | Method and composition for mounting an electronic component and device formed therewith A method of mounting a component on a substrate includes applying a conductive adhesive on a contact pad joined to a substrate, aligning a component with the substrate such that at least one lead of the component is juxtaposed with the conductive adhesive... | 07/08/2003 |
| 6590285 | Method and composition for mounting an electronic component and device formed therewith A method of mounting a component on a substrate includes applying a conductive adhesive on a contact pad joined to a substrate, aligning a component with the substrate such that at least one lead of the component is juxtaposed with the conductive adhesive... | 07/08/2003 |
| 6586683 | Printed circuit board with mixed metallurgy pads and method of fabrication A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set o... | 07/01/2003 |
| 6581821 | Electronic package interconnect structure comprising lead-free solders A method and structure for forming an electronic package with an interconnect structure that comprises lead-free solders. The method first forms a module by initially providing a chip carrier, a first joiner solder that is lead-free, and a core interconne... | 06/24/2003 |
| 6583517 | Method and structure for joining two substrates with a low melt solder joint A method and structure to electrically and mechanically join a first a first electrically conductive pad on a first substrate to a second electrically conductive pad on a second substrate using a solder joint that includes a low-melt solder alloy composit... | 06/24/2003 |
| 6574860 | Ball grid array module The method according to a preferred embodiment of the present invention mitigates the problem of gold contamination during the SMT assembly operations in the manufacture of Hybrid Multi Chip Modules (HMCM), achieving a high assembly process yield. This ta... | 06/10/2003 |
| 6576549 | Fabrication of a metalized blind via A method and structure for forming a metalized blind via. A dielectric layer is formed on a metallic layer, followed by laser drilling a depression in the dielectric layer such that a carbon film that includes the carbon is formed on a sidewall of the dep... | 06/10/2003 |
| 6576996 | Method for bonding heat sinks to overmolds and device formed thereby A method for bonding heat sinks to packaged electronic components comprises the steps of: (a) exposing to a plasma a surface of a molded polymer formed on a substrate; (b) allowing the plasma to at least partially convert silicon-containing residue on the... | 06/10/2003 |
| 6559388 | Strain relief for substrates having a low coefficient of thermal expansion An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a soldered interface, such as a solder ball or a solder column, between a chip carrier (or chip) and an electronic carrier such as a circuit card. The ... | 05/06/2003 |
| 6552266 | High performance chip packaging and method A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included.... | 04/22/2003 |
| 6552264 | High performance chip packaging and method A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included.... | 04/22/2003 |
| 6545869 | Adjusting fillet geometry to couple a heat spreader to a chip carrier An electronic structure, and associated method of fabrication, for coupling a heat spreader above a chip to a chip carrier below the chip. Initially provided is a substrate, a chip on a surface of the substrate and coupled to the substrate, and the heat s... | 04/08/2003 |
| 6541981 | Automation of transmission line pulse testing of electrostatic discharge devices A method and apparatus for automated testing of a plurality of electrostatic discharge (ESD) devices on a wafer. The wafer has M padsets and N conductive pads on each padset, where m is at least 1, and n is at least 2, and each ESD device is conductively ... | 04/01/2003 |
| 6541847 | Packaging for multi-processor shared-memory system An electrical structure or package, and associated method of formation. A plurality of logic chips is coupled electrically to a memory chip either through conductive members (e.g., solder balls) that interface with the memory chip and each logic chip, or ... | 04/01/2003 |
| 6541857 | Method of forming BGA interconnections having mixed solder profiles A method of forming BGA interconnections having improved fatigue life is disclosed. In particular, a combination of mask-defined and pad-defined solder joints are selectively positioned within the BGA package. The mask-defined solder joints possess a high... | 04/01/2003 |
| 6537608 | Protection of a plated through hole from chemical attack A method of forming an electronic structure, including adhesively coupling a plated metallic layer (e.g. a copper layer) of a plated through hole (PTH) to holefill material (e.g., epoxy resin) distributed within the PTH. The adhesive coupling utilizes an ... | 03/25/2003 |
| 6538213 | High density design for organic chip carriers An organic integrated circuit chip carrier for high density integrated circuit chip attach, wherein the contact pads or microvias which provide electrical interconnections to external circuitry are located in a first array pattern, while the plated throug... | 03/25/2003 |
| 6534848 | Electrical coupling of a stiffener to a chip carrier A method and structure for conductively coupling a metallic stiffener to a chip carrier. A substrate has a conductive pad on its surface and an adhesive layer is formed on the substrate surface. The metallic stiffener is placed on the adhesive layer, wher... | 03/18/2003 |
| 6534160 | Semiconductor device having a thermoset-containing dielectric material and methods for fabricating the same A semiconductor device having a thermoset-containing, dielectric material and methods for fabricating the same is provided. The device may take the form of a printed circuit board, an integrated circuit chip carrier, or the like. The dielectric material i... | 03/18/2003 |
| 6530412 | Surface mount technology with masked cure A method for temporarily attaching an electrical component to a pad, testing the component, removing and replacing the component if necessary, and making a final attachment of the component to the pad. The method provides for attachment and removal of com... | 03/11/2003 |
| 6522014 | Fabrication of a metalized blind via A method and structure for forming a metalized blind via. A dielectric layer is formed on a metallic layer, followed by laser drilling a depression in the dielectric layer such that a carbon film that includes the carbon is formed on a sidewall of the dep... | 02/18/2003 |
| 6521844 | Through hole in a photoimageable dielectric structure with wired and uncured dielectric An electronic structure. The electronic structure comprises a layer. The layer includes: a cylindrical volume; a fully cured annular volume of a photoimageable dielectric (PID) material circumscribing the cylindrical volume; and a partially cured remainin... | 02/18/2003 |
| 6521842 | Hybrid surface mount and pin thru hole circuit board A multi-layer circuit board is disclosed. The circuit board comprises a plurality of conductive planes; a plurality of plated through hole sets, each set comprising one or more plated through holes, none to all of the plated through holes of each set cont... | 02/18/2003 |
| 6518509 | Copper plated invar with acid preclean An electronic structure that includes a copper-Invar-copper (CIC) laminate of negligible thickness, such as a thickness not exceeding about 0.5 microns. The electronic structure may have a via passes through the CIC laminate such that the via is plated wi... | 02/11/2003 |
| 6518516 | Multilayered laminate A multilayered laminate, substructures and associated methods of fabrication are presented. The multilayered laminate includes in sequential order: (a) a first intermediate layer having microvias and conductive lands; (b) a plurality of signal/power plane... | 02/11/2003 |
| 6504111 | Solid via layer to layer interconnect The present invention relates to a structure for providing an interconnect between layers of a multilayer circuit board. The structure comprises a stack that includes at least one layer and a via opening that extends through at least one layer of the stac... | 01/07/2003 |
| 6499644 | Rework and underfill nozzle for electronic components A method and apparatus for desoldering electronic components from a substrate. A vacuum is used to enhance the flow of a hot gas under an electronic component to reflow the solder connections attaching the electronic component to a substrate. Water vapor ... | 12/31/2002 |
| 6497943 | Surface metal balancing to reduce chip carrier flexing A surface metal balancing structure for a chip carrier, and an associated method of fabrication, to reduce or eliminate thermally induced chip carrier flexing. A substrate, such as a chip carrier made of organic dielectric material, is formed and includes... | 12/24/2002 |
| 6495772 | High performance dense wire for printed circuit board A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wir... | 12/17/2002 |
| 6492600 | Laminate having plated microvia interconnects and method for forming the same A chip carrier structure and method for forming the same having a receptor pad formed therein. The structure comprises a circuitized substrate having a conductive element on the surface, an External Dielectric Layer mounted on the circuitized substrate wi... | 12/10/2002 |
| 6492724 | Structure for reinforcing a semiconductor device to prevent cracking A structure and methods for reinforcing a semiconductor device to prevent cracking is provided. The device may take the form of a semiconductor chip or a semiconductor chip package. When a semiconductor chip is provided, an adhesion layer is applied over ... | 12/10/2002 |
| 6488153 | Cushioning member A cushioning member with three interconnecting parts provides a full internal corner for contacting and protecting the external surfaces of an article during shipping and handling. The three interconnecting parts also provide a full external corner. Both ... | 12/03/2002 |
| 6483074 | Laser beam system for micro via formation A laser system for micro via formation directly over a plated through hole (PTH). The laser system forms the micro via directly over the PTH with full dielectric removal from a capture pad while minimizing the dielectric removal from a center portion of t... | 11/19/2002 |
| 6483046 | Circuit board having burr free castellated plated through holes The present invention provides a circuit board having burr free castellated plated through holes. In particular, the leading edge of the plated through hole, that tends to produce burr formation during conventional profiling, is removed or pre-profiled to... | 11/19/2002 |
| 6464080 | Cushioning structure A cushioning structure for placement between an impacting surface and a surface of an object to be cushioned against damage caused by impact during transport, storage, or usage, comprising a spring member having a load bearing portion and spring lead port... | 10/15/2002 |
| 6464125 | Rework and underfill nozzle for electronic components A method and apparatus for desoldering electronic components from a substrate. A vacuum is used to enhance the flow of a hot gas under an electronic component to reflow the solder connections attaching the electronic component to a substrate. Water vapor ... | 10/15/2002 |
| 6462285 | Wave solder application for ball grid array modules with plugged vias A method and product for fabricating a printed circuit board assembly comprising a via, wherein the method inhibits the flow of molten solder into the via during a wave soldering step, thereby preventing heat transfer that might otherwise degrade a solder... | 10/08/2002 |
| 6457631 | Rework and underfill nozzle for electronic components A method and apparatus for desoldering electronic components from a substrate. A vacuum is used, to enhance the flow of a hot gas under an electronic component to reflow the solder connections attaching the electronic component to a substrate. Water vapor... | 10/01/2002 |
| 6453537 | Cooling method for electronic components A method for cooling electrical components on a substrate during a rework process. A block of a porous, thermally conductive material, saturated with a liquid, is positioned on an electrical component to be cooled. During the rework processing of an adjac... | 09/24/2002 |
| 6436803 | Manufacturing computer systems with fine line circuitized substrates Circuit boards are manufactured by forming a substrate with a dielectric surface and laminating a metal foil onto the substrate. The metal foil is patterned to form a first wiring layer. A permanent photoimagable dielectric layer is formed over the wiring... | 08/20/2002 |
