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| Number | Title | Issue Date |
| 5095302 | Three dimensional mouse via finger ring or cavity A cursor control/data input device for a computer display system which utilizes a conventional X-Y mouse provided with a third Z with axis data generating mechanism. The mouse may be used with any non-specific support surface and would have conventional X... | 03/10/1992 |
| 5051736 | Optical stylus and passive digitizing tablet data input system A stylus and table X-Y data input system for a video display system. The pen includes an optical styling having a suitable pickup mechanism and the tablet is passive in nature and provides direct digitized data readout. Absolute positional information is ... | 09/24/1991 |
| 4969088 | Hardware mechanism for automatically detecting hot-spot references and diverting same from memory traffic in a multiprocessor computer system An interconnection network management architecture for use with a large shared memory multiprocessor computing system including a plurality of processors and a plurality of separately addressable main memory modules. Two parallel, interconnection networks... | 11/06/1990 |
| 4868549 | Feedback mouse A mouse for use in a video display system for controlling cursor movement on a display screen provided with feedback means which produces resistance to the motion of the mouse as the cursor moves across predetermined areas of the display screen. In its mo... | 09/19/1989 |
| 4774688 | Data processing system for determining min/max in a single operation cycle as a result of a single instruction A data processing system is provided which includes ALU data busses, temporary operand storage registers, an accumulator, and a set of latches for temporarily storing data to be supplied to the input of the ALU. Output multiplexer is provided which can se... | 09/27/1988 |
| 4763255 | Method for generating short form instructions in an optimizing compiler A method for improving the quality of code generated by a compiler or assembler, for a target machine that has short and long forms of some of its instructions with the short forms executing faster or occupying less space. The method first determines whic... | 08/09/1988 |
| 4763289 | Method for the modeling and fault simulation of complementary metal oxide semiconductor circuits A method for modeling complementary metal oxide semiconductor (CMOS) combinatorial logic circuits by Boolean gates taking into account circuit behavior effects due to charge storing and static hazards. Models are developed for both the faultless and fault... | 08/09/1988 |
| 4742471 | Method for improving wirability of master-image DCVS chips A method for increasing the wirability of complementary metal oxide semiconductor (CMOS) differential cascode voltage switch (DCVS) logic circuits which comprises designing the circuitry to permit as many of the internal tree connections as possible to be... | 05/03/1988 |
| 4719568 | Hierarchical memory system including separate cache memories for storing data and instructions A hierarchical memory system for use with a high speed data processor characterized by having separate dedicated cache memories for storing data and instructions and further characterized by each cache having a unique cache directory containing a pluralit... | 01/12/1988 |
| 4712916 | Apparatus for inspection of the walls of deep holes of minute diameter The inspection of the walls of a deep hole of minute diameter in a structure such as an integrated circuit board is carried out by inserting into the hole a reflective optical sphere having a diameter at least slightly smaller than the hole diameter. A co... | 12/15/1987 |
| 4675843 | Programmable logic controller The programmable logic controller uses a set of instructions which comprises only three instructions: a Read instruction and a Write instruction which includes an operation code, a condition bit, and an address, and a Jump instruction which includes an op... | 06/23/1987 |
| 4656583 | Method for improving global common subexpression elimination and code motion in an optimizing compiler A method for use during the optimizatin phase of an optimizing compiler for performing global common subexpression elimination and code motion which comprises: Determining the code `basis` for the object program which includes examining each basic block o... | 04/07/1987 |
| 4656582 | Generating storage reference instructions in an optimizing compiler A method for improving the quality of code generated by a compiler in terms of execution time, object code space, or both. The method is applicable to computers that have a redundancy of instructions, in that the same operation exists in forms that operat... | 04/07/1987 |
| 4644344 | Electrochromic matrix display An electrochromic matrix display of the kind in which the display electrodes are supported on a substrate above a corresponding matrix of transistor switches employs constant current writing and potentiostatic erasure. The transistors are switchable by si... | 02/17/1987 |
| 4644503 | Computer memory system with integrated parallel shift circuits The system includes a plurality of memory units each for storing a plurality of independently addressable binary bits. The units operate together in response to each common bit address to supply a bit from each unit to form an array of bits for a discrete... | 02/17/1987 |
| 4642764 | Method of developing formal identities and program bases in an optimizing compiler A method operable within an optimizing compiler for generating Basis items and Kill Sets for use during subsequent global common subexpressions elimination and code motion procedures. More particularly, the method comprises assigning a symbolic register t... | 02/10/1987 |
| 4642765 | Optimization of range checking A method operable within an optimizing compiler to move certain range check instructions out of single entry strongly connected regions or loops and into linear regions of the instruction stream whereby computational efficiency is increased with no loss o... | 02/10/1987 |
| 4638426 | Virtual memory address translation mechanism with controlled data persistence A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly efficient and versatile manner and for controlling certain memory ... | 01/20/1987 |
| 4637853 | Hollow cathode enhanced plasma for high rate reactive ion etching and deposition A metallic hollow cathode electrode structure for use in a RF-RIE sputter/etch system. The electrode defines a critical aspect ratio hollow cathode volume. In accordance with one embodiment of the invention, the electrode structure may consist of two clos... | 01/20/1987 |
| 4633129 | Hollow cathode A long life high current density hollow cathode electron beam source for use in various E-beam apparatus which uses an ionizable gas within the hollow cathode. Bombardment of an electron emissive surface within the hollow cathode by energetic gas ions cau... | 12/30/1986 |
| 4617646 | Electric field gradient excited liquid crystal cell having bistability A liquid crystal storage device includes a smectic phase liquid crystalline medium in spaced relationship with at least three separated electrodes, the first of which provides a ground plane and is in contact with the liquid crystal medium; a second elect... | 10/14/1986 |
| 4611272 | Key-accessed file organization A key-accessed (indexed) file is organized such that the file structure consists only of two levels, an index level and a data level. Both levels are permanently stored on a page-organized secondary storage medium that supports random accessing of the pag... | 09/09/1986 |
| 4588490 | Hollow cathode enhanced magnetron sputter device A plasma sputter etching/deposition system comprising an electron-emitting hollow cathode arc-source combined with a conventional plasma sputter etching/deposition system such as a magnetron. The electrons emitted are coupled into the intrinsic high energ... | 05/13/1986 |
| 4589087 | Condition register architecture for a primitive instruction set machine A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more comple... | 05/13/1986 |
| 4589065 | Mechanism for implementing one machine cycle executable trap instructions in a primitive instruction set computing system A mechanism for performing a run-time storage address validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly... | 05/13/1986 |
| 4587629 | Random address memory with fast clear A technique and apparatus for augmenting a random access memory with a fast clear or reset mechanism are described. A dynamic RAM having a fast clear mechanism in accordance with the present invention includes means for coupling a digital signal onto all ... | 05/06/1986 |
| 4571678 | Register allocation and spilling via graph coloring In an optimizing compiler which receives a high level source language program and produces machine interpretable instructions, a method for assigning computational data utilized by the program to a limited number of high speed machine registers in a targe... | 02/18/1986 |
| 4569016 | Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system A mechanism for performing fast and efficient full shift, merge, insert and bit alignment functions within one operating machine cycle of a host primitive instructions set computing system. In general, the circuitry performs a ring shift under control of ... | 02/04/1986 |
| 4562592 | Shifting technique for signature verification A signature verification system includes means for obtaining acceleration data and pressure data related to a given signature and means for comparing that data with reference data previously obtained from an identified signer. The correlations between seg... | 12/31/1985 |
| 4553258 | Segmentation algorithm for signature vertification A signature verification method is based on a comparison of the dynamics of a reference and a sample signature. Acceleration and pressure signals produced by a known person when writing his or her signature are stored and used as a reference signals. Then... | 11/12/1985 |
| 4553259 | Semi-independent shifting technique for signature verification A signature verification system includes means for obtaining acceleration data and pressure data related to a given signature and means for comparing that data with reference data previously obtained from an identified signer. The correlations between seg... | 11/12/1985 |
| 4539506 | Red-emitting superlinear phosphor In a red-emitting phosphor which includes ZnSe as a host material, copper (Cu) as an activator and aluminum (Al) as a coactivator, the improvement comprising the inclusion of a small amount of cobalt (Co) to provide superlinear characteristics to said pho... | 09/03/1985 |
| 4538240 | Method and apparatus for performing hashing operations using Galois field multiplication The invention comprises a method and apparatus for performing a hashing operation on an N bit number under control of a prespecified N bit hashing constant which comprises performing N/K finite field partial multiplications of the object to be hashed by t... | 08/27/1985 |
| 4526441 | Method and electrolytic display for selectively displaying an image An image is displayed in an electrolytic display by the reversible deposition on electrodes having non-scattering surfaces of a deposit having light scattering properties. The deposit scatters incident light out of the specular direction and the image is ... | 07/02/1985 |
| 4513437 | Data input pen for Signature Verification A writing implement having special applicability for use as a pressure and acceleration sensitive element for use in a Signature Verification System. The pen structure includes both a writing implement for making a visible record and also includes unique ... | 04/23/1985 |
| 4488142 | Apparatus for encoding unconstrained data onto a (1,7) format with rate 2/3 An algorithm and the hardware embodiment for producing a run length limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of 1 zero and a maximum of 7 zeros between adjacent 1's. The... | 12/11/1984 |
| 4486739 | Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code A binary DC balanced code and an encoder circuit for effecting same is described, which translates an 8 bit byte of information into 10 binary digits for transmission over electromagnetic or optical transmission lines subject to timing and low frequency c... | 12/04/1984 |
| 4463344 | Method and apparatus for generating a noiseless sliding block code for a (2,7) channel with rate 1/2 An algorithm and the hardware embodiment for producing a run length limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of 2 zeros and a maximum of 7 zeros between adjacent 1's. Th... | 07/31/1984 |
| 4447048 | Symmetrical three degree of freedom compliance structure A symmetrical three-degree of freedom compliant structure specifically adapted for use in robotic manipulators interposed between a movable robotic arm and the gripper fingers. The structure is uniquely adapted to serve as both a force sensing device and ... | 05/08/1984 |
| 4437149 | Cache memory architecture with decoding An information processing unit and storage system comprising at least one low speed, high capacity main memory having relatively long access time and including a plurality of data pages stored therein and at least one high speed, low capacity Cache memory... | 03/13/1984 |
