Bizarre Patents
Mouthguard made at least partially from an edible candy
A mouthguard includes a U-shaped upper bite plate which removably fits over upper teeth of a person, with the entire upper bite plate being made from a soft, deformable and edible gummi candy.
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| Number | Title | Issue Date |
| 4949169 | Audio-video data interface for a high speed communication link in a video-graphics display window environment An interface architecture for interconnecting a plurality of video display devices together over a high speed digital communication link having limited bandwidth provides at each node for transmitting during a "transmit mode"; (1) sequential pixels of dig... | 08/14/1990 |
| 4947316 | Internal bus architecture employing a simplified rapidly executable instruction set An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture of the internal bus mechanism defines a... | 08/07/1990 |
| 4925700 | Process for fabricating high density disc storage device A process for forming chromium dioxide thin films which are receptive to high density magnetic recording. The process comprises depositing both chromium and oxygen on a substrate by evaporative techniques and concurrently bombarding the substrate with hig... | 05/15/1990 |
| 4905188 | Functional cache memory chip architecture for improved cache access An on-chip VLSI cache architecture including a single-port, last-select, cache array organized as an n-way set-associative cache (having n congruence classes) including a plurality of functionally integrated units on-chip in addition to the cache array an... | 02/27/1990 |
| 4903217 | Frame buffer architecture capable of accessing a pixel aligned M by N array of pixels on the screen of an attached monitor A frame buffer memory organization which is capable of accessing a pixel aligned M by N array of contiguous pixels on the screen from a frame buffer memory constructed of an M by N array of memory chips by driving a common address bus to all the memory ch... | 02/20/1990 |
| 4903196 | Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor A method and apparatus for controlling access to its general purpose registers (GPRs) by a high end machine configuration including a plurality of execution units within a single CPU. The invention allows up to "N" execution units to be concurrently execu... | 02/20/1990 |
| 4885680 | Method and apparatus for efficiently handling temporarily cacheable data A method and apparatus for marking data that is temporarily cacheable to facilitate the efficient management of said data. A bit in the segment and/or page descriptor of the data called the marked data bit (MDB) is generated by the compiler and included i... | 12/05/1989 |
| 4824544 | Large area cathode lift-off sputter deposition device An etching/deposition system comprising a hollow cathode electron source in combination with a magnetron sputter deposition plasma device within a containment chamber, said hollow cathode being disposed to inject electrons into the magnetic field of the m... | 04/25/1989 |
| 4823286 | Pixel data path for high performance raster displays with all-point-addressable frame buffers A multichannel data path architecture which assists a host processor in communication with the frame buffer in order to increase the overall system performance. The architecture provides automatic frame buffer data path rearrangement depending on the pixe... | 04/18/1989 |
| 4816814 | Vector generator with direction independent drawing speed for all-point-addressable raster displays A vector generator for us with an all-points-addressable frame buffer capable of the non-word aligned access, simultaneously, of a square M by N array of pixels providing fast vector drawing independently of vector slope and position in the whole screen a... | 03/28/1989 |
| 4802091 | Method for improving the efficiency of arithmetic code generation in an optimizing compiler using the technique of reassociation A procedure for use in an optimizing compiler termed "reassociation" determines the preferred order of combining terms in a sum so as to produce loop invariant subcomputations, or to promote common subexpressions among several essential computations, by a... | 01/31/1989 |
| 4691277 | Small instruction cache using branch target table to effect instruction prefetch A branch target table (10) is used as an instruction memory which is referenced by the addresses of instructions which are targets of branches. The branch target table consists of a target address table (12), a next fetch address table (14), valid entries... | 09/01/1987 |
| 4663729 | Display architecture having variable data width A display architecture is disclosed which supports a variable, selectable number of bits per chip and a variable, selectable segment width. The architecture comprises a plurality of dynamic memory chips and a function generator. Each of the memory chips i... | 05/05/1987 |
| 4573199 | Kanji/Chinese font generation by scaling A method of data compression which allows an enlarged font of complex characters to be produced by scaling from data representing a stored font of complex characters is disclosed. The scaling procedure involves the insertion of horizontal and vertical lin... | 02/25/1986 |
| 4382286 | Method and apparatus for compressing and decompressing strings of electrical digital data bits A compression technique for a character graphics system in which character cell definition bit strings are transmitted from a central processing unit to a display unit. Each cell is divided into a number of slices and each slice into digits. A test is mad... | 05/03/1983 |
| 4369463 | Gray scale image data compression with code words a function of image history The present invention relates to a method and apparatus for compacting gray-scale image data which maintains extremely good picture quality and can result in typical images in a compression ratio of 5 to 1 and even better if a final step of arithmetic cod... | 01/18/1983 |
| 4344171 | Effective error control scheme for satellite communications A hybrid scheme for controlling transmission errors in digital data communication systems. Normally, data blocks with a small number of parity digits for error detection are transmitted. When the presence of errors is detected, the retransmissions are not... | 08/10/1982 |
| 4330845 | Guess-ahead feature for a keyboard-display terminal data input system A guess-ahead feature for an interactive terminal having a keyboard and a display screen where input data is entered via the keyboard and displayed. Means are provided for continually evaluating input data to determine if it is the beginning of a string o... | 05/18/1982 |
| 4330858 | Time domain supervisory channel for data terminal equipments Digital data communication system uses a common channel to carry both normal messages and supervisory messages, the latter being inserted into the message stream during intervals between normal messages. Each transmitting location has a switch or equivale... | 05/18/1982 |
| 4328555 | Apparatus for computing two-dimensional discrete Fourier transforms An apparatus for computing the two-dimensional discrete Fourier transform (DFT) of an image comprised of N×N samples. The samples within each row are respectively multiplied by W-n.sbsp.1, n1 =0, 1, . . . , N-1 and stored in a memor... | 05/04/1982 |
| 4326098 | High security system for electronic signature verification The system provides both electronic signature and message verification with a minimum of excess coding information on an instantaneous basis and is easily restartable in a store and forward environment. The system is based on the concept of a vault or cen... | 04/20/1982 |
| 4316055 | Stream/block cipher crytographic system The system disclosed comprises a dual function cryptographic system capable of operating in either a stream or block cipher mode. Further, with minimal alteration the system is capable of performing either encoding or decoding functions. The system requir... | 02/16/1982 |
| 4312066 | Diagnostic/debug machine architecture A system is described for enabling the connection of a diagnostic/debugging processor to another host processor for the purpose of troubleshooting that processor's hardware and software. The system is composed of an interface between the diagnostic/debugg... | 01/19/1982 |
| 4302810 | Method and apparatus for secure message transmission for use in electronic funds transfer systems An electronic funds transfer system wherein it is required that a bank be reasonably guaranteed that the two parties to a retail transaction (i.e., a person and a retailer) agree on the transaction before the funds transfer takes place. The message includ... | 11/24/1981 |
| 4295039 | Method and apparatus for achieving secure password verification A method and apparatus for identifying an individual holder (person) of an unalterable charge card-like device (CARD) at a utilization terminal (U/I Terminal) wherein a unique user entered key (asserted key KA) is handled in a highly secure man... | 10/13/1981 |
| 4277837 | Personal portable terminal for financial transactions A personal portable terminal for financial transactions adapted for use with one or more data storage and transfer cards (DSTCs) and other external devices, such as point of sale terminals, is disclosed. The transaction device includes keyboard means for ... | 07/07/1981 |
| 4274139 | Digital telecommunication network having improved data processing systems A plurality of digital data processing systems are interconnected as nodes in a telecommunication network. When two intelligent nodes are conneected and one local node determines that a process which it is executing requires the use of resources held at t... | 06/16/1981 |
| 4264782 | Method and apparatus for transaction and identity verification A method and apparatus whereby the senders and receivers of messages sent over a transmission system including a Host CPU may guarantee the integrity of the data content of the message and also the absolute identity of the sender. Each user of the system ... | 04/28/1981 |
| 4255811 | Key controlled block cipher cryptographic system A cryptographic system for encrypting a block of binary data under the control of a key consisting of a set of binary symbols. The cryptographic system may be utilized within a data processing environment to ensure complete privacy of data and information... | 03/10/1981 |
| 4244048 | Chip and wafer configuration and testing method for large-scale-integrated circuits A chip-testing method, which allows Large-Scale-Integrated circuit (LSI) logic chips to be tested on wafer without necessitating expensive equipment involving high-precision step-and-repeat mechanisms, and which further allows chips to be tested individua... | 01/06/1981 |
| 4229818 | Method and apparatus for enciphering blocks which succeed short blocks in a key-controlled block-cipher cryptographic system A method and apparatus for providing improved error-recovery and cryptographic strength when enciphering blocks which succeed short blocks in a Key-Controlled Block-Cipher Cryptographic System with chaining. Beginning with a pre-existing current chaining ... | 10/21/1980 |
| 4223403 | Cryptographic architecture for use with a high security personal identification system A Cryptographic Architecture for improving the security of Cash-Issuing or similar Terminal Systems when it is necessary to operate Off-Host. Each Terminal is connected to a central Controller which is in turn connected to a central Host. The Master crypt... | 09/16/1980 |
| 4195200 | Key controlled block-cipher cryptographic system employing a multidirectional shift matrix A cryptographic system for enciphering a block of binary data under the control of a unique key consisting of a set of binary symbols. A clear message represented in binary data format is transformed into a cipher message (and vise versa) by operating on ... | 03/25/1980 |
| 4195196 | Variant key matrix cipher system This is a cipher system for enciphering a stream of binary data by means of a product cipher. A clear message represented in a binary data format is transformed into a cipher message by operating on each bit of clear information with a complex modulo-two ... | 03/25/1980 |
| 4156920 | Computer system architecture for performing nested loop operations to effect a discrete Fourier transform A computer system architecture and method for performing the Discrete Fourier Transform on a set of N sampled input signals wherein N is chosen to be the product of a group of predetermined relatively prime factors (n1 .multidot.n2 .... | 05/29/1979 |
| 4149218 | Minimum delay module assembly A Minimum Delay Module Assembly, having unrestricted accessibility for servicing, that provides substantially constant electrical and thermal environments for all portions of the assembly regardless of configuration. The assembly comprises a plurality of ... | 04/10/1979 |
| 4142175 | Pressure sensing device and transducer arrangement A pressure sensing device having applicability as a simple pressure sensor and which is particularly adapted for use as a pen in a Signature Verification System, said device including a unique mounting structure for the pressure sensing stylus by flexible... | 02/27/1979 |
| 4128829 | Signature verification method and apparatus utilizing both acceleration and pressure characteristics Method and apparatus are disclosed for verifying a sample signature based on comparison of the dynamics of a reference and a sample signature. More particularly, second derivative values of pen displacements (i.e. acceleration) and continuous pressure pat... | 12/05/1978 |
| 4104721 | Hierarchical security mechanism for dynamically assigning security levels to object programs A computer system organization which allows a program to specify a predetermined security level for other programs which it invokes, while at the same time being subject to security restraints placed on it either by a higher priority level invoking progra... | 08/01/1978 |
| 4087856 | Location dependence for assuring the security of system-control operations A computer operating system security mechanism employing a non-penetrable hardware means for storing privileged instruction identification data for preventing direct unauthorized access to certain privileged instructions forming a part of the computer ope... | 05/02/1978 |
