Bizarre Patents
Crispy Chip Sandwich and Process of Producing a Sandwich Product
A food product comprising a multilayer cookie or snack having outer layers formed from a crispy type edible food product such as a potato chip or corn chip, etc. with an intermediate marshmallow layer being in contact with the inner surface of each crispy chip and one or more filler substances.
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| Number | Title | Issue Date |
| 6829760 | Runtime symbol table for computer programs A method 100, an apparatus, and a computer program product for constructing a runtime symbol table SymTbl[ ] for a computer program are disclosed. In the method, a symbol table SymTbl[ ] for storing one or more entities Ei is initialized 110. | 12/07/2004 |
| 6823507 | Detection of memory-related errors in computer programs A method, an apparatus, and a computer program product are disclosed for detecting memory-related errors in a computer program during compiling of the computer program. In the method, static analysis is performed upon a computer program. One or more conditions in th... | 11/23/2004 |
| 6791940 | Method and apparatus for data transmission control in a computer network environment A data network may comprise routers for transmitting data between locations in the network via alternative routes. A network gateway or server may normally send data packets to a particular default router but, for network communication recovery, the gateway needs to... | 09/14/2004 |
| 6721945 | Optimization of calls in programming languages using pointers for passing reference parameters A method and computer program product for executing procedure calls, such as procedure calls in the C programing language. For a procedure call, reference parameters are identified, and replaced by respective scalar variables. The scalar values are propagated to a c... | 04/13/2004 |
| 6721785 | System for directing e-mail to selected recipients by applying transmission control directives on aliases identifying lists of recipients to exclude or include recipients This invention relates to a method, apparatus and program product for transmitting email to selected recipients defined by one or more aliases in identified lists of recipients, by providing transmission control directives given by the user, parsing the said directi... | 04/13/2004 |
| 6654836 | Dual master device for improved utilization of a processor local bus A dual master apparatus for mastering a Processor Local Bus (PLB), which is a high-performance, on-chip bus used in many System on Chip (SOC) applications, supporting up to 16 masters. The apparatus includes a first circuit for generating an address phase... | 11/25/2003 |
| 6651248 | Method and apparatus for efficient interface method dispatch The interface method invocation mechanism of the present invention includes an interface method table (IMT) for a given class of objects. The IMT comprises a table of entries each corresponding to a set S of interface methods that are implemented by objec... | 11/18/2003 |
| 6634023 | Compile method, exception handling method and computer The present invention enables re-ordering of instructions to be executed while assuring a precise exception. In Java language, an optimization process of re-ordering instructions to be executed is performed by Just-In-Time compiler. For instance, the inst... | 10/14/2003 |
| 6529962 | Preserving thread identity during remote calls A method for performing remote calls between source and target computing machines includes running a program thread on the source machine which invokes a remote call to the target machine. The remote call is transmitted to the target machine, the call inc... | 03/04/2003 |
| 6501895 | Optical device with a defined total device stress and method for manufacturing it An optical device with a defined total device stress (ς10) and a therefrom resulting defined birefringence in order to obtain a well defined optical polarization dependence is proposed. It comprises a lower cladding layer (3) with a first refr... | 12/31/2002 |
| 6384833 | Method and parallelizing geometric processing in a graphics rendering pipeline The geometric processing of an ordered sequence of graphics commands is distributed over a set of processors by the following steps. The sequence of graphics commands is partitioned into an ordered set of N subsequences S0 . . . SN-1... | 05/07/2002 |
| 6236958 | Method and system for extracting pairs of multilingual terminology from an aligned multilingual text A terminology extraction system which allows for automatic creation of bilingual terminology has a source text which comprises at least one sequence of source terms, aligned with a target text which also comprises at least one sequence of target terms. A ... | 05/22/2001 |
| 5508859 | Gravity feed data storage library having magnetic picker An automated storage library having the ability to store and manipulate data storage elements in three dimensions. Data storage elements such as tape cartridges are stored in storage compartments separated by low-friction downward sloping sliding planes e... | 04/16/1996 |
| 5245485 | Multiple tape thickness, multiple recording format tape drive systems The invention is one or more tape systems which determine the length of tapes mounted therein to assess the thickness of such tapes. A format identifier is written at one of a plurality of locations on the tape depending upon the tape thickness. The forma... | 09/14/1993 |
| 5198933 | Recording medium emergency release mechanism The invention is an information reproduction apparatus provided with supporting means for supporting a recording medium, a drive source for moving the recording medium between the initial insertion position and the reproduction position by driving said su... | 03/30/1993 |
| 5159597 | Generic error recovery An error recovery subsystem which can be easily modified for use with any physical hardware which is being monitored is disclosed. The error recovery subsystem employs a user editable file including the rules for defining the system state, the error state... | 10/27/1992 |
| 5101409 | Checkboard memory self-test The invention is a system and method for high-efficiency checkerboard memory self-test. A random pattern generator configuration includes a linear feedback shift register and a multiple input signature register. The random pattern generator is used to ste... | 03/31/1992 |
| 5080825 | Tape drive cleaning composition A water based cleaning composition suitable for use in tape drives including very small quantities of a surfactant, preferably a tridecyl alcohol ether of polyoxyethylene, and an ionic salt of ammonia is disclosed. The quantity of surfactant is such that ... | 01/14/1992 |
| 5051366 | Electrical connector An electrical connector including a top clamp plate, two circuit bars, a resilient pressure pad, a bottom clamp plate, and means for fastening two flexible circuits and a third circuit device in mating electrical contact therein is disclosed. Each flexibl... | 09/24/1991 |
| 4974156 | Multi-level peripheral data storage hierarchy with independent access to all levels of the hierarchy A peripheral data storage hierarchy includes three storage levels. The top storage level is a fast accessing direct access storage device(s), such as magnetic disk drives. The intermediate level is an automatic warehouse type library, storing a large plur... | 11/27/1990 |
| 4967301 | Shallow magnetic head shield for reducing feedthrough A magnetic head is disclosed in which thin strips of shielding are inlaid into the surface of the magnetic head between the read and write gaps for reducing feedthrough. The shielding extends across a substantial portion of the tape-engaging surface betwe... | 10/30/1990 |
| 4945428 | Method of managing a media library A data storage hierarchy includes a media library characterized by a travelling elevator which moves in front of an open-faced wall of storage cells or compartments and ingress-egress slots to a plurality of data recording devices. Optical disks are selec... | 07/31/1990 |
| 4903266 | Memory self-test A system and method for on-chip self test of memory circuits is disclosed. Memory circuit testing is accomplished by using a random pattern generator based upon a primitive polynomial and including a linear feedback shift register having at least one stag... | 02/20/1990 |
| 4844616 | Interferometric dimensional measurement and defect detection method The invention is a method for detecting both surface topography and defect presence using an AC interferometer. Surface topography measurements are maximized by adjusting the signal voltage of the light modulator to a relative phase-sensitive value. Defec... | 07/04/1989 |
| 4845379 | Sense circuit for detecting absence of a pulse train A low-cost circuit capable of detecting the absence of a pulse train such as the pulse train generated by a fan cooling output circuit of open collector design. The detection circuit is capable of sensing that a pulse output has stopped in either a high o... | 07/04/1989 |
| 4837680 | Controlling asynchronously operating peripherals A plurality of host processors share access to a peripheral data storage subsystem and each have program means for controlling asynchronous operations of the subsystem. Control blocks in each of the host processors are addressably linked together for enab... | 06/06/1989 |
| 4805142 | Multiple ROM data state, read/write memory cell A read/write memory cell is disclosed in which multiple ROM data states can be stored. Independent sensing of the resistance values of each of two resistors accounts for the storage of multiple ROM data states. The resistors are encompassed in a pair of c... | 02/14/1989 |
| 4734175 | Process for regenerating an electroless copper plating bath A process and an apparatus are described for regenerating an electroless copper plating bath containing a complexing agent, preferably ethylenediamine tetraacetic acid. From the bath solution to be regenerated, the copper content is reduced by electrolysi... | 03/29/1988 |
| 4703409 | Coupled power supply inductors for reduced ripple current A power supply circuit for producing at least one output which is essentially free from current ripple is disclosed. A chopped DC voltage source is applied to a transformer having a primary coil and at least two secondary coils. The secondary coils provid... | 10/27/1987 |
