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| Number | Title | Issue Date |
| 5943494 | Method and system for processing multiple branch instructions that write to count and link registers A system and method for processing count and link branch instructions that allows multiple branches to be outstanding at the same time without being limited to the number of rename registers allocated to the count and link registers. The method and system... | 08/24/1999 |
| 5822755 | Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache A microprocessor architecture including a first cache memory disposed on-chip for storing data along with an associated on-chip tag memory. A second memory is provided on-chip for storing data in a first mode of operation and for storing tags relating to ... | 10/13/1998 |
| 5822556 | Distributed completion control in a microprocessor A distributed completion control system for a microprocessor is disclosed. The system comprises a plurality of dispatch units, each of the dispatch units further comprises a dispatch queue responsive to a fetched address for receiving instructions; a plur... | 10/13/1998 |
| 5758140 | Method and system for emulating instructions by performing an operation directly using special-purpose register contents A system and method for improving the performance of a processor that emulates a guest instruction where the guest instruction includes a first and second operand. The first operand is stored in a general purpose register, and the second operand is stored... | 05/26/1998 |
| 5751946 | Method and system for detecting bypass error conditions in a load/store unit of a superscalar processor A method for detecting bypass error conditions in a load/store unit of a superscalar processor includes determining whether a load instruction has executed out-of-order with respect to an executing store instruction when a real address to a word boundary ... | 05/12/1998 |
| 5751945 | Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system A method for identifying bottlenecks within a processing system, the processing system including a plurality of performance monitor counters (PMCs) and at least one monitor mode control register (MMCR) to configure the operations of at least one of the PM... | 05/12/1998 |
| 5742784 | System for reordering of instructions before placement into cache to reduce dispatch latency A method and system for reducing the dispatch latency of instructions of a processor provides for reordering the instructions in a predetermined format before the instructions enter the cache. The method and system also stores information in the cache rel... | 04/21/1998 |
| 5737636 | Method and system for detecting bypass errors in a load/store unit of a superscalar processor A load queue is provided in a load/store unit of a superscalar processor that includes a real page number buffer for storing a real page number for each instruction entry in the load queue. The load queue also includes a real page number comparator couple... | 04/07/1998 |
| 5732235 | Method and system for minimizing the number of cycles required to execute semantic routines A system and method for reducing the cycle time necessary to execute semantic routines in a processor that emulates guest instructions. Each of the semantic routines includes a block of host instructions for performing the function of the corresponding gu... | 03/24/1998 |
| 5729726 | Method and system for performance monitoring efficiency of branch unit operation in a processing system A method and system for determining the effectiveness of operation of a branch of a branch unit in a processing system the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to ... | 03/17/1998 |
| 5729501 | High Speed SRAM with or-gate sense A system and method for replacing sense amplifiers used in conventional RAMS with domino circuits in order to create a domino static random access memory. The domino SRAM of the present invention is created through extensive partitioning of conventional b... | 03/17/1998 |
