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Reward Candy Dispenser for Personal Computers
A personal computer peripheral, battery powered reward candy dispenser which immediately presents students with a single candy for each problem completed correctly.
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| Number | Title | Issue Date |
| 7725446 | Commitment of transactions in a distributed system A method for committing transactions in a distributed system are provided. The method provides for receiving a request from a client to commit a transaction at a coordinator node in the distributed system, tracking a tail log sequence number for every other node in ... | 05/25/2010 |
| 7714640 | No-trim low-dropout (LDO) and switch-mode voltage regulator circuit and technique An optimized output voltage circuit and technique obtainable without trimming is set forth. A voltage reference circuit and method devoid of trim resistors comprising a high gain amplifier, a plurality of bandgap resistors, and at least a plurality of bipolar device... | 05/11/2010 |
| 7711730 | Method of returning data during insert statement processing A method for generating an execution plan for updating and retrieving data from a database in a single process includes: receiving a statement by a server to update a database with a first set of data and to retrieve a second set of data from the database; building ... | 05/04/2010 |
| 7689435 | Method and apparatus for creating and managing complex business processes A method and apparatus are disclosed for managing composite business processes that include multiple trading mechanisms, such as requests for quotes (RFQs), auctions and contracts, or repeat passes through a single trading mechanism. The independence of the individu... | 03/30/2010 |
| 7680821 | Method and system for index sampled tablescan An optimized query processing system and method for a database system. The database system includes a table of data and an index correlated to both the query and to the table. The optimized query processing system includes an index accessing module adapted to access... | 03/16/2010 |
| 7659783 | System and method for phase-locked loop (PLL) for high-speed memory interface (HSMI) A phase-locked loop (PLL) to provide clock generation for high-speed memory interface is presented as the innovate PLL (IPLL). The IPLL architecture is able to tolerate external long loop delay without deteriorating jitter performance. The IPLL comprises in part a c... | 02/09/2010 |
| 7635621 | Lateral double-diffused metal oxide semiconductor (LDMOS) device with an enhanced drift region that has an improved Rarea product A lateral double-diffused metal oxide semiconductor (LDMOS) device is disclosed. The LDMOS device comprises a gate region and a body region under the gate region. The LDMOS device includes an enhanced drift region under the gate region. The enhanced drift region tou... | 12/22/2009 |
| 7627484 | Method and apparatus for managing and displaying user authorizations for a business process managed using a state machine A method and apparatus are disclosed for managing access control for a business process that is managed using a state machine. A domain represents the various trading mechanisms that are supported by a business process. Domains are placed at the highest level in a t... | 12/01/2009 |
| 7619475 | Cancellation of common mode oscillation in RF circuits A multistage RF amplifier amplifies RF signals used for communication in a WLAN communications system. The multistage RF amplifier comprises a first amplifier circuit coupled to a second amplifier circuit to maximize amplification. A common mode of the first amplifi... | 11/17/2009 |
| 7608907 | LDMOS gate controlled schottky diode An improved diode is disclosed. The diode comprises a Schottky diode and a LDMOS device coupled in series with the Schottky diode. In a preferred embodiment, a forward current from the Schottky diode is allowed to flow through the channel of a depletion mode LDMOS t... | 10/27/2009 |
| 7606166 | System and method for computing a blind checksum in a host ethernet adapter (HEA) A system and method for computing a blind checksum includes a host Ethernet adapter (HEA) with a system for receiving a packet. The system determines whether or not the packet is in Internet protocol version four (IPv4). If the packet is not in IPv4, the system comp... | 10/20/2009 |
| 7594630 | Mounting fixture for a peripheral device A mounting fixture for a computer peripheral is disclosed. The fixture comprises a mounting member adapted to be coupled to the peripheral; and a magnet coupled to the mounting member. The magnet couples the fixture to a housing. Accordingly, a mounting fixture is p... | 09/29/2009 |
| 7593155 | Active temporal modulation of ultrashort pulse trains using reconfigurable optical gratings A system and method for the temporal and phase modulation of beams through a series of electronically controlled grating modulators, as acousto optic devices (AODs), is provided where incoming electromagnetic radiation may be advanced or retarded by introducing a ti... | 09/22/2009 |
| 7589567 | Compensation technique for current source channel-length modulation A circuit is provided that includes a current source, and a compensation circuit to generate a compensation current based on an output voltage of the current source. The circuit further includes a combiner to combine the compensation current with an output current o... | 09/15/2009 |
| 7586936 | Host Ethernet adapter for networking offload in server environment An Ethernet adapter is disclosed. The Ethernet adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a demultiplexing mechanism to allow for partitioning of the proce... | 09/08/2009 |
| 7583724 | Low-power mixed-mode echo/crosstalk cancellation in wireline communications A signal processing system includes an AGC and pre-echo cancellation system for receiving an analog signal, amplifying signal magnitude (over all frequencies) to a pre-determined level by AGC, and removing the immediate transmit pulse from this received signal by pr... | 09/01/2009 |
| 7577891 | Method and apparatus for extending decoding time in an iterative decoder using input codeword pipelining A decoder architecture and method for implementing a decoder are provided. In one implementation, the decoder architecture includes an input buffer configured to receive a plurality of codewords to be processed, and includes an iterative decoder configured to receiv... | 08/18/2009 |
| 7577151 | Method and apparatus for providing a network connection table Method and apparatus for implementing use of a network connection table. In one aspect, searching for network connections includes receiving a packet, and zeroing particular fields of connection information from the packet if a new connection is to be established. T... | 08/18/2009 |
| 7576390 | System for vertical DMOS with slots A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the s... | 08/18/2009 |
| 7574621 | Method and system for identifying and recovering a file damaged by a hard drive failure A method and system for identifying and recovering a file damaged by a hard drive failure. The method includes monitoring event logs, mapping at least one failing sector to at least one corresponding corrupted file if a hard drive failure is detected, and performing... | 08/11/2009 |
| 7573714 | Method and apparatus for dissipating heat in a computer system A cooling system for a computer is provided. In one implementation, the cooling system includes a heat spreader that is in thermal contact with a heat generating component in the computer, a frame casting, and a heat pipe to passively dissipate heat generated from t... | 08/11/2009 |
| 7572707 | Method of manufacturing NPN device A method of forming a semiconductor device is disclosed. The method includes providing a floor for a semiconductor device by utilizing a CMOS process. The method further includes providing a BiCMOS-like process on top of the floor to further fabricate the semiconduc... | 08/11/2009 |
| D592196 | Pan/tilt tracking mount | 05/12/2009 |
