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| Number | Title | Issue Date |
| 6122638 | Object-oriented processor and method for caching intermediate data in an object-oriented processor An object-oriented processor and method of operating such a processor are disclosed. According to the method, in response to receiving a first instruction that references a first object having both data and at least a first method associated therewith, an... | 09/19/2000 |
| 6067603 | Non-uniform memory access (NUMA) data processing system that speculatively issues requests on a node interconnect A computer system includes a node interconnect to which at least a first processing node and a second processing node are coupled. The first and the second processing nodes each include a local interconnect, a processor coupled to the local interconnect, ... | 05/23/2000 |
| 6067611 | Non-uniform memory access (NUMA) data processing system that buffers potential third node transactions to decrease communication latency A non-uniform memory access (NUMA) computer system includes an interconnect to which multiple processing nodes (including first, second, and third processing nodes) are coupled. Each of the first, second, and third processing nodes includes at least one p... | 05/23/2000 |
| 6035390 | Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical operation A processor includes at least an execution unit that executes an instruction by performing an operation indicated by the instruction utilizing one or more operands and condition code logic that determines less than, greater than, and equal to condition co... | 03/07/2000 |
| 5995743 | Method and system for interrupt handling during emulation in a data processing system A processor and method of interrupt handling in a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, in response to occurrence of an interrupt during emulatio... | 11/30/1999 |
| 5991708 | Performance monitor and method for performance monitoring within a data processing system The present invention provides a performance monitor including a threshold indicator, a granularity indicator, an event detector, and an event counter. The threshold indicator indicates a number of threshold increments, which each correspond to a number o... | 11/23/1999 |
| 5987598 | Method and system for tracking instruction progress within a data processing system A processor and method for tracking instruction execution within a processor are described. The processor includes at least one execution unit that executes instructions and an instruction status indicator that dynamically indicates a status of an instruc... | 11/16/1999 |
| 5961639 | Processor and method for dynamically inserting auxiliary instructions within an instruction stream during execution A processor and method of executing a program within a processor are provided. According to the method, a plurality of program instructions comprising a program and a set of auxiliary instructions are stored. An instruction stream including selected ones ... | 10/05/1999 |
| 5956495 | Method and system for processing branch instructions during emulation in a data processing system A series of guest instructions including at least one guest branch instruction and other guest instructions are stored in memory. In addition, one or more semantic routines that are formed of native instructions and that may be utilized to emulate the ser... | 09/21/1999 |
| 5953520 | Address translation buffer for data processing system emulation mode A processor and method of operating a processor which has a native instruction set and emulates instructions in a guest instruction set are described. According to the method, a series of guest instructions from the guest instruction set are stored in mem... | 09/14/1999 |
| 5913054 | Method and system for processing a multiple-register instruction that permit multiple data words to be written in a single processor cycle A processor and method of processing a multiple-register instruction are described. The processor includes execution circuitry and a set of registers, which are each capable of storing a data word. A multiple-register instruction specifying a plurality of... | 06/15/1999 |
| 5901307 | Processor having a selectively configurable branch prediction unit that can access a branch prediction utilizing bits derived from a plurality of sources A processor and method for speculatively executing a branch instruction are disclosed. The processor includes a branch prediction unit for predicting a resolution of a speculative branch instruction, which is selectively configurable such that resolution ... | 05/04/1999 |
| 5897654 | Method and system for efficiently fetching from cache during a cache fill operation A method and system in a data processing system for efficiently interfacing with cache memory by allowing a fetcher to read from cache memory while a plurality of data words or instructions are being loaded into the cache. A request is made by a bus inter... | 04/27/1999 |
| 5889947 | Apparatus and method for executing instructions that select a storage location for output values in response to an operation count A multiprocessor computer system comprises a plurality of processors, wherein each processor includes an execution unit, a program counter, a result buffer containing a plurality of entries, each entry being allocated to hold an output value of an instruc... | 03/30/1999 |
| 5887166 | Method and system for constructing a program including a navigation instruction A method and system are provided for constructing a program executable by a processor including one or more processing elements for executing threads and a thread scheduler for assigning threads to the processing elements for execution. According to the m... | 03/23/1999 |
| 5875294 | Method and system for halting processor execution in response to an enumerated occurrence of a selected combination of internal states A method and system within a data processing system are disclosed for halting execution of instructions by a processor in response to an enumerated occurrence of a selected combination of internal states within the processor. The processor includes a numb... | 02/23/1999 |
| 5873123 | Processor and method for translating a nonphysical address into a physical address utilizing a selectively nonsequential search of page table entries A processor and method for translating a nonphysical address into a physical address are disclosed. A determination is made if a first entry set which could contain a particular entry that associates a selected nonphysical address with a corresponding phy... | 02/16/1999 |
| 5872948 | Processor and method for out-of-order execution of instructions based upon an instruction parameter A processor and method for out-of-order execution of instructions are disclosed which fetch a first and a second instruction, wherein the first instruction precedes the second instruction in a program order. A determination is made whether execution of th... | 02/16/1999 |
| 5870575 | Indirect unconditional branches in data processing system emulation mode A processor and method of operating a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, a series of guest instructions including at least one unconditional i... | 02/09/1999 |
| 5850563 | Processor and method for out-of-order completion of floating-point operations during load/store multiple operations A method and apparatus in a superscalar microprocessor for early completion of floating-point instructions prior to a previous load/store multiple instruction is provided. The microprocessor's load/store execution unit loads or stores data to or from the ... | 12/15/1998 |
| 5809526 | Data processing system and method for selective invalidation of outdated lines in a second level memory in response to a memory request initiated by a store operation A method and system of enhancing memory performance in a data processing system are provided. The data processing system may include a processor having an on-board first-level cache, a second-level cache coupled to the processor, a system bus coupled to t... | 09/15/1998 |
| 5805475 | Load-store unit and method of loading and storing single-precision floating-point registers in a double-precision architecture A floating point numbers load-store unit includes a translator for converting between the single-precision and double-precision representations, and Special-Case logic for providing Special-Case signals when a store is being performed on zero, infinity, o... | 09/08/1998 |
| 5765215 | Method and system for efficient rename buffer deallocation within a processor A method and system are disclosed for managing the deallocation of a rename buffer allocated to an update instruction within a processor. The processor has a number of rename buffers for temporarily storing information associated with instructions execute... | 06/09/1998 |
