Saile; George O., Pike; Rosemary L. S., Stoffel; William J. - US Patent Attorneys and Agents

Attorney: Saile; George O., Pike; Rosemary L. S., Stoffel; William J.

Number of patents: 37
Last date: April 01, 2003

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Number	Title	Issue Date
6541327	Method to form self-aligned source/drain CMOS device on insulated staircase oxide A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard m...	04/01/2003
6534390	Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structure The present invention provides an improved semiconductor device of a Silicon/Amorphous Silicon/Metal Structure (SASM) and a method of making an improved semiconductor device by a salicide process by using an anneal to form a thick silicide film on shallow...	03/18/2003
6495200	Method to deposit a seeding layer for electroless copper plating A method of for electroless copper deposition using a Pd/Pd acetate seeding layer formed in using only two components (Pd acetate and solvent) to form an interconnect for a semiconductor device. The invention has two preferred embodiments. The first embod...	12/17/2002
6472697	Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level co...	10/29/2002
6468880	Method for fabricating complementary silicon on insulator devices using wafer bonding A method to form a silicon on insulator (SOI) device using wafer bonding. A first substrate is provided having an insulating layer over a first side. A second substrate is provided having first isolation regions (e.g., STI) that fill first trenches in the...	10/22/2002
6460404	Apparatus and method for detecting bad edge bead removal in a spin-on-glass coater tool A solvent delivery system for an edge bead removal tool (EBR) that detects N2 leaks in a solvent pressure tank that surrounds a solvent bottle. A solvent bottle is surrounded by a pressure tank. The solvent bottle contains the solvent used in t...	10/08/2002
6440800	Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conduct...	08/27/2002
6436770	Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A d...	08/20/2002
6417054	Method for fabricating a self aligned S/D CMOS device on insulated layer by forming a trench along the STI and fill with oxide A method for a self aligned TX with elevated source/drain (S/D) regions on an insulated layer (oxide) by forming a trench along side the STI and filling the trench with oxide. STI regions are formed in a substrate. A gate structure is formed. LDD regions ...	07/09/2002
6406945	Method for forming a transistor gate dielectric with high-K and low-K regions A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is form...	06/18/2002
6399471	Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level co...	06/04/2002
6380088	Method to form a recessed source drain on a trench side wall with a replacement gate technique An improved MOS transistor and method of making an improved MOS transistor. An MOS transistor having a recessed source drain on a trench sidewall with a replacement gate technique. Holes are formed in the shallow trench isolations, which exposes sidewall ...	04/30/2002
6372569	Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performance A method of selective formation of SiN layer in a semiconductor device comprising the following steps. A semiconductor structure having at least one PMOS transistor and one NMOS transistor formed therein is provided. The PMOS and NMOS transistors each hav...	04/16/2002
6313008	Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed in the barrier layer. Next, ions are implanted into said ...	11/06/2001
6309982	Method for minimizing copper diffusion by doping an inorganic dielectric layer with a reducing agent A method for reducing copper diffusion into an inorganic dielectric layer adjacent to a copper structure by doping the inorganic dielectric layer with a reducing agent (e.g. phosphorous, sulfur, or both) during plasma enhanced chemical vapor deposition. T...	10/30/2001
6306714	Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide A method of fabrication of an elevated source/drain (S/D) for a MOS device. A first insulating layer having a gate opening and source/drain openings is formed over a substrate. We form a LDD resist mask having opening over the source/drain openings over t...	10/23/2001
6306715	Method to form smaller channel with CMOS device by isotropic etching of the gate materials A method to form a MOS transistor with a narrow channel regions and a wide top (second) gate portion. A gate dielectic layer and a first gate layer are formed over a substrate. A second gate portion is formed over the first gate layer. Spacers are formed ...	10/23/2001
6303447	Method for forming an extended metal gate using a damascene process A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, ...	10/16/2001
6303458	Alignment mark scheme for Sti process to save one mask step A method of fabrication an alignment mark in a semiconductor device. The method uses one mask to that has two functions (1) a reverse active areas mask to remove the oxide from over active areas in the device areas and (2) an alignment mark open mask that...	10/16/2001
6303449	Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP A method of manufacturing a self aligned elevated source/drain (S/D). A first insulating layer is formed over a substrate. The first insulating layer having at least a gate opening and source/drain (S/D) openings adjacent to the gate opening. Spacer porti...	10/16/2001
6294480	Method for forming an L-shaped spacer with a disposable organic top coating A method for forming an L-shaped spacer using a sacrificial organic top coating. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner o...	09/25/2001
6287979	Method for forming an air gap as low dielectric constant material using buckminsterfullerene as a porogen in an air bridge or a sacrificial layer A method for reducing RC delay by forming an air gap between conductive lines. A sacrificial layer is formed over a semiconductor structure, filling the gaps between conductive lines on the semiconductor structure. An air bridge layer is formed over the s...	09/11/2001
6284613	Method for forming a T-gate for better salicidation A method for a T-gate and salicide process that allows narrow bottom gate widths below 0.25 μm and wide top gate widths to allow silicide gate contacts on the top of the T-gate. A dummy gate composed of an insulating material is formed over the substrate...	09/04/2001
6277700	High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness A method of etching silicon nitride spacers beside a gate structure comprising: providing a gate electrode over a gate oxide layer on a substrate. A liner oxide layer is provided over the substrate and the gate electrode. A silicon nitride layer is provid...	08/21/2001
6258676	Method for forming a shallow trench isolation using HDP silicon oxynitride A Method for forming a shallow trench isolation using HDP silicon oxynitride. A pad oxide layer is formed on a semiconductor substrate having an active area and an isolation area and a barc layer is formed over the pad oxide layer. The barc layer, the pad...	07/10/2001
6248618	Method of fabrication of dual gate oxides for CMOS devices A method of forming thick and thin gate oxides comprising the following steps. A silicon semiconductor substrate having first and second active areas separated by shallow isolation trench regions is provided. Oxide growth is selectively formed over the fi...	06/19/2001
6228713	Self-aligned floating gate for memory application using shallow trench isolation A method to make a self-aligned floating gate in a memory device. The method patterns the floating gate (FG) using the trench etch for the shallow trench isolation (STI). Because the floating gate (FG) is adjacent to the raised STI, sharp corners are elim...	05/08/2001
6197705	Method of silicon oxide and silicon glass films deposition A method for fabricating a silicon oxide and silicon glass layers at low temperature using soft power-optimized Plasma-Activated CVD with a TEOS-ozone-oxygen reaction gas mixture (TEOS O3 /O2 PACVD) is described. It combines advantag...	03/06/2001
6187633	Method of manufacturing a gate structure for a semiconductor memory device with improved breakdown voltage and leakage rate The invention is a method of manufacturing a semiconductor memory device using a novel intergate dielectric stack. A key feature of of the invention is the novel O/N/SiON/O structure, forming a silicon oxynitride layer on the silicon nitride layer. The me...	02/13/2001
6165891	Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer A method and structure for forming a damascene structure with reduced capacitance by forming one or more of: the passivation layer, the etch stop layer, and the cap layer using a low dielectric constant material comprising carbon nitride, boron nitride, o...	12/26/2000
6156598	Method for forming a lightly doped source and drain structure using an L-shaped spacer A method for forming an L-shaped spacer using a sacrificial organic top coating, then using the L-shaped spacer to simultaneously implant lightly doped source and drain extensions through the L-shaped spacer while implanting source and drain regions beyon...	12/05/2000
6153485	Salicide formation on narrow poly lines by pulling back of spacer A method for a salicide process where S/D silicide contacts are formed in a separate silicide step than the gate silicide contacts. Preferably, TiSi2 is formed on S/D regions and TiSi2 or CoSi2 is formed on Poly electrodes...	11/28/2000
6103569	Method for planarizing local interconnects A method for planarizing metal plugs for device interconnections. The process begins by providing a semiconductor structure with at least one device thereon. A dielectric layer is formed over the device and the semiconductor structure. A first barrier met...	08/15/2000
6090691	Method for forming a raised source and drain without using selective epitaxial growth A method for forming a raised source and drain structure without using selective epitaxial silicon growth. A semiconductor substrate is provided having one or more gate areas covered by dielectric structures. Doped polysilicon structures are adjacent to t...	07/18/2000
6063547	Physical vapor deposition poly-p-phenylene sulfide film as a bottom anti-reflective coating on polysilicon A method of patterning conductive lines using a bottom anti-reflective coating (BARC) composed of Poly-p-phenylene sulfide (PPS) film 30 formed using a Physical Vapor Deposition (PVD) process. The PPS BARC 30 is easy to remove and has superior planarizati...	05/16/2000
6063702	Global planarization method for inter level dielectric layers using IDL blocks The present invention provides a method of manufacturing of planarizing an insulating layer using a reduced size reversed interconnect mask and an etch stop layer. Spaced interconnections 22 are provided over the semiconductor substrate 10. An etch stop l...	05/16/2000
5930646	Method of shallow trench isolation The invention is an improved process for forming isolations of uniform thickness in narrow and wide trenches. The process begins by forming a pad layer on a semiconductor substrate. A first barrier layer is formed on the pad layer. The first barrier layer...	07/27/1999

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Attorney: Saile; George O., Pike; Rosemary L. S., Stoffel; William J.