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| Number | Title | Issue Date |
| 6689653 | Method of preserving the top oxide of an ONO dielectric layer via use of a capping material Methods of protecting, and increasing the thickness of, the oxidized silicon nitride (ON), component of an oxidized silicon nitride on silicon oxide (ONO), layer of a non-volatile memory device, during the hydrofluoric (HF), acid type procedures used for ... | 02/10/2004 |
| 6689643 | Adjustable 3D capacitor There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual c... | 02/10/2004 |
| 6586309 | High performance RF inductors and transformers using bonding technique A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurali... | 07/01/2003 |
| 6586143 | Accurate wafer patterning method for mass production A method for checking the position of alignment marks after a chemical mechanical polishing (CMP) process and automatically compensating for alignment of a wafer stepper based on the position checking is described. A wafer is provided having an alignment ... | 07/01/2003 |
| 6586314 | Method of forming shallow trench isolation regions with improved corner rounding A method of forming a shallow trench isolation (STI), region in a semiconductor substrate featuring a process sequence that results in desired rounded corners for the sides of active device regions located butting the STI region, has been developed. The p... | 07/01/2003 |
| 6583069 | Method of silicon oxide and silicon glass films deposition A method for fabricating a silicon oxide and silicon glass layers at low temperature using High Density Plasma CVD with silane or organic or inorganic silane derivatives as a source of silicon, inorganic compounds containing boron, phosphorus, and fluorin... | 06/24/2003 |
| 6583011 | Method for forming damascene dual gate for improved oxide uniformity and control A method to grow layers of gate oxide or gate base materials of different thicknesses for dual gate structures. The process starts with a semiconductor surface in which STI regions have been formed and over the surface of which a layer of gate base materi... | 06/24/2003 |
| 6576526 | Darc layer for MIM process integration A new processing sequence is provided for the creation of a MIM capacitor. The process starts with the deposition of a first layer of metal. Next are deposited listed, a thin layer of metal, a layer of insulation, a second layer of metal and a layer of An... | 06/10/2003 |
| 6572731 | Self-siphoning CMP tool design for applications such as copper CMP and low-k dielectric CMP A new method is provided for the polishing of semiconductor surfaces such as the surface of a substrate, the surface of deposited copper and the surface of low-k layers of dielectric. The polishing method and apparatus of the invention comprise a new slur... | 06/03/2003 |
| 6569699 | Two layer mirror for LCD-on-silicon products and method of fabrication thereof A method of fabricating an LCD-on-silicon pixel device including the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling t... | 05/27/2003 |
| 6569762 | Three dimensional IC package module In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to... | 05/27/2003 |
| 6566215 | Method of fabricating short channel MOS transistors with source/drain extensions A novel method for forming short channel MOS transistors is described. A hard mask stack is formed over a substrate. A first opening is formed through a top portion of the hard mask stack. Oxide spacers are formed on sidewalls of the first opening thereby... | 05/20/2003 |
| 6566650 | Incorporation of dielectric layer onto SThM tips for direct thermal analysis One of the limitations to current usage of scanning thermal microscopes arises when one needs to obtain a thermal map of an electrically biased specimen. Current practice is for the conductive parts of the specimen to be passivated to prevent excessive cu... | 05/20/2003 |
| 6565664 | Method for stripping copper in damascene interconnects An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by v... | 05/20/2003 |
| 6566208 | Method to form elevated source/drain using poly spacer A method for forming a sub-quarter micron MOSFET having an elevated source/drain structure is described. A gate electrode is formed over a gate dielectric on a semiconductor substrate. Ions are implanted into the semiconductor substrate to form lightly do... | 05/20/2003 |
| 6566209 | Method to form shallow junction transistors while eliminating shorts due to junction spiking A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first ele... | 05/20/2003 |
| 6566260 | Non-metallic barrier formations for copper damascene type interconnects A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly... | 05/20/2003 |
| 6558739 | Titanium nitride/titanium tungsten alloy composite barrier layer for integrated circuits A method for forming a barrier layer upon an electrode contact. There is first provided a silicon substrate layer having an electrode contact region formed within the silicon substrate layer. There is then formed over the silicon substrate layer a titaniu... | 05/06/2003 |
| 6554560 | Method for aligning wafers in a cassette A wafer orienting apparatus for aligning a plurality of semiconductor wafers each of which has a v-notch formed on its outer periphery. The apparatus includes a cassette process carrier for supporting the plurality of wafers in parallel wafer supporting s... | 04/29/2003 |
| 6555878 | Umos-like gate-controlled thyristor structure for ESD protection Described is a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMO... | 04/29/2003 |
| 6552399 | Dummy layer diode structures for ESD protection Described are structures for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks. A controllable dummy layer diode is provided which is struct... | 04/22/2003 |
| 6547652 | Linear CMP tool design using in-situ slurry distribution and concurrent pad conditioning An apparatus for multiple component slurry distribution during semiconductor wafer polishing operations. Concurrent polishing pad conditioning is obtained by means of a novel polishing pad design where polishing pads are mounted in a cylindrical configura... | 04/15/2003 |
| 6548231 | Enhanced passivation scheme for post metal etch clean process A two step passivation procedure, used to remove chlorine from polymer layers formed on the sides of metal structures, prior to removal of the defining photoresist shape, and of the polymer layers, has been developed. The procedure features a first passiv... | 04/15/2003 |
| 6540841 | Method and apparatus for removing contaminants from the perimeter of a semiconductor substrate A new method and apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals a... | 04/01/2003 |
| 6538333 | Three dimensional IC package module In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to... | 03/25/2003 |
| 6534393 | Method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity A method for making low sheet resistance local metal interconnections and improved transistor performance is described. The method involves patterning a polysilicon layer and a silicon nitride (Si3 N4) cap layer over device areas to ... | 03/18/2003 |
| 6535098 | Integrated helix coil inductor on silicon A new structure and method is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of a helix coil design having upper level and lower level conductors further having an axis whereby the axis of the... | 03/18/2003 |
| 6534388 | Method to reduce variation in LDD series resistance A process used to retard out diffusion of P type dopants from P type LDD regions, resulting in unwanted LDD series resistance increases, has been developed. The process features the formation of a nitrogen containing layer, placed between the P type LDD r... | 03/18/2003 |
| 6528420 | Double acting cold trap A double acting cold trap equipped with a set of exhaust gas condensing fins and a set of exhaust gas condensing plates is disclosed. The invention also discloses a double acting cold trap that incorporates a deflecting plate to direct the exhaust gases o... | 03/04/2003 |
| 6524963 | Method to improve etching of organic-based, low dielectric constant materials A method etching an organic-based, low dielectric constant material in the manufacture of an integrated circuit device has been achieved. Organic materials without silicon and organic materials without fluorine can be etched by using, for example, hydrazi... | 02/25/2003 |
| 6524910 | Method of forming dual thickness gate dielectric structures via use of silicon nitride layers A process for forming a first group of gate structures, designed to operate at a lower voltage than a simultaneously formed second group of gate structures, has been developed. The process features the thermal growth of a first silicon dioxide gate insula... | 02/25/2003 |
| 6521540 | Method for making self-aligned contacts to source/drain without a hard mask layer An improved and new process for fabricating self-aligned contacts (SAC) to source/drain areas of complimentary (CMOS) FET's has been developed using a non-conformal layer of silicon nitride, eliminating the need for a hard mask. This process allows for "z... | 02/18/2003 |
| 6521079 | Linear CMP tool design with closed loop slurry distribution An apparatus for closed loop slurry distribution during semiconductor wafer polishing operations. The traditional peristaltic pump for slurry supply is eliminated thus eliminating irregularities in the conventional slurry supply. Common platform mounting ... | 02/18/2003 |
| 6517235 | Using refractory metal silicidation phase transition temperature points to control and/or calibrate RTP low temperature operation A method for controlling and/or calibrating rapid thermal process systems is described. One or more wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon are silicided in a RTP system at different temperatures. Sheet ... | 02/11/2003 |
| 6513374 | Apparatus to quantify the adhesion of film A new apparatus is provided for the quantification of the adhesion of a film over a substrate. In particular, the peeling force and the rate of peeling are quantified by providing a first means for measuring the peeling force, a second means for measuring... | 02/04/2003 |
| 6501122 | Flash device having a large planar area ono interpoly dielectric A new method of fabricating a stacked gate Flash EEPROM device having an improved interpoly oxide layer is described. A gate oxide layer is provided on the surface of a substrate. A first polysilicon layer is deposited overlying the gate oxide layer and p... | 12/31/2002 |
| 6500771 | Method of high-density plasma boron-containing silicate glass film deposition A method for fabricating a boron-contained silicate glass layers, such as borosilicate and borophosphosilicate glass films at low temperature using High Density Plasma CVD with silane derivatives as a source of silicon, boron and phosphorus compounds as a... | 12/31/2002 |
| 6498635 | Method of forming insulating material alignment posts associated with active device structures The invention teaches a method of forming an improved liquid-crystal-on-silicon display. The device structure is enhanced by the creation of silicon nitride alignment posts using methods of photolithography, the alignment posts are located among the pixel... | 12/24/2002 |
| 6492726 | Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection In accordance with the objectives of the invention a new package is provided that is provided with a cavity that is shaped such that more than one semiconductor device can in a vertical direction be mounted in the cavity of the package. The devices that a... | 12/10/2002 |
| 6492242 | Method of forming of high K metallic dielectric layer A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding ... | 12/10/2002 |
