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| Number | Title | Issue Date |
| 6608362 | Method and device for reducing capacitive and magnetic effects from a substrate by using a schottky diode under passive components A method of fabricating high quality passive components having reduced capacitive and magnetic effects by using a Schottky diode underlying the passive components in the manufacture of integrated circuits is described. A Schottky diode is formed completel... | 08/19/2003 |
| 6587178 | Device structure that combines insulating materials for alignment posts and optical interference layers A method of forming an improved liquid-crystal-on-silicon display and resultant display is described, in which the device structure is enhanced by the photolithography building of alignment posts among the mirror pixels of the microdisplay.... | 07/01/2003 |
| 6569770 | Method for improving oxide erosion of tungsten CMP operations A new method to prevent oxide erosion in a metal plug process by employing a silicon nitride layer over the oxide is described. An oxide layer is deposited overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the oxide layer... | 05/27/2003 |
| 6548413 | Method to reduce microloading in metal etching A new method of etching metal lines with reduced microloading effect is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered with an insulating layer. A barrier metal layer is deposited overlying the insu... | 04/15/2003 |
| 6544848 | Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers A new method of forming a sharp tip on a floating gate in the fabrication of a EEPROM memory cell is described. A first gate dielectric layer is provided on a substrate. A second gate dielectric layer is deposited overlying the first gate dielectric layer... | 04/08/2003 |
| 6531390 | Non-metallic barrier formations for copper damascene type interconnects A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly... | 03/11/2003 |
| 6468853 | Method of fabricating a shallow trench isolation structure with reduced local oxide recess near corner A structure and a process for manufacturing semiconductor devices with improved oxide coverage on the corners of a shallow trench isolation structure is described. The STI trench is etched using a pad oxide and silicon nitride layers as patterning element... | 10/22/2002 |
| 6465888 | Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene A method of forming amorphous silicon spacers followed by the forming of metal nitride over the spacers in a copper damascene structure--single, dual, or multi-structure--is disclosed in order to prevent the formation of fluorides in copper. In a first em... | 10/15/2002 |
| 6465157 | Dual layer pattern formation method for dual damascene interconnect A new method of forming dual damascene interconnects has been achieved. A semiconductor substrate is provided. A dielectric layer is provided overlying the semiconductor substrate. A first photoresist layer is deposited overlying the dielectric layer. The... | 10/15/2002 |
| 6455781 | Thermocouple ceramic bead insulator An improved thermocouple having a ceramic bead insulator is described. A pair of wires in parallel is joined at a first end to a thermocouple and joined at a second end to a connector. The pair of wires is threaded through each of a series of interlocking... | 09/24/2002 |
| 6439977 | Rotational slurry distribution system for rotary CMP system An apparatus for slurry distribution during semiconductor wafer polishing operations. The slurry is gravity fed or fed under pressure and broadcast under an angle across the entire face of the polishing pad by either a rotating slurry nozzle arrangement o... | 08/27/2002 |
| 6417544 | Diode-like plasma induced damage protection structure A novel structured for a diode-like PID protection (DLPP) device structure and process are described. An N-well, three associate N+ regions and a P+ region are formed on a P substrate. The DLPP is structured as a butting diode with a polysilicon gate abov... | 07/09/2002 |
| 6403484 | Method to achieve STI planarization A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the... | 06/11/2002 |
| 6399431 | ESD protection device for SOI technology A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. A silicon-on-insulator substrate is provided comprising a semiconductor substrate underlying an oxide layer underlying a silicon layer. The silicon ... | 06/04/2002 |
| 6380084 | Method to form high performance copper damascene interconnects by de-coupling via and metal line filling A method to form robust dual damascene interconnects by decoupling via and connective line trench filling has been achieved. A first dielectric layer is deposited overlying a silicon nitride layer. A shielding layer is deposited. The shielding layer, the ... | 04/30/2002 |
| 6291307 | Method and structure to make planar analog capacitor on the top of a STI structure A new method is provided to create a capacitor over the surface of STI regions. The STI regions are first created in the surface of the substrate, a layer of sacrificial oxide is next blanket deposited over the substrate (thereby including the surface of ... | 09/18/2001 |
| 6284603 | Flash memory cell structure with improved channel punch-through characteristics A new method of fabricating a Flash EEPROM memory cell is achieved. Ions are optionally implanted into said semiconductor substrate to form threshold enhancement regions of the same type as the semiconductor substrate. A tunneling oxide is formed. A first... | 09/04/2001 |
| 6268276 | Area array air gap structure for intermetal dielectric application A new method of forming air gaps between adjacent conducting lines of a semiconductor circuit by using a "holes everywhere" or a "reverse metal holes" mask that can be used to create holes in a dielectric layer. The dielectric that is being etched has bee... | 07/31/2001 |
| 6251798 | Formation of air gap structures for inter-metal dielectric application A method for the formation of an air gap structure for use in inter-metal applications. A metal pattern of metal lines is formed, a layer of Plasma Polymerized Methylsilane (PPMS) resist is deposited on top of this pattern. The surface of the PPMS resist ... | 06/26/2001 |
| 6251786 | Method to create a copper dual damascene structure with less dishing and erosion A dual damascene structure is created in a dielectric layer, the structure contains a barrier layer while a cap layer may or may not be provided over the layer of dielectric for further protection of the dual damascene structure. The surface of the copper... | 06/26/2001 |
| 6221560 | Method to enhance global planarization of silicon oxide surface for IC device fabrication A new method for planarizing silicon dioxide surfaces in semiconductor structures. Starting with a structure of an underlying layer (for instance a layer of metal lines) a layer of oxide is deposited and profiled by positive tone imaging. A layer of PPMS ... | 04/24/2001 |
| 6214680 | Method to fabricate a sub-quarter-micron MOSFET with lightly doped source/drain regions A new method of fabricating a MOSFET device is described. A semiconductor substrate is provided and isolation areas are formed isolating active areas in the substrate. An oxide layer is provided overlying both the substrate and isolation area and is patte... | 04/10/2001 |
| 6216092 | Dosage monitor for deionized water generator An apparatus and method are described for determining precisly when the resin column in a deionized water generator needs to be regenerated. This is achieved by causing the untreated water to pass through a flowmeter and by measuring its electrical conduc... | 04/10/2001 |
| 6207534 | Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing A method of forming trenches having different depths for use in shallow trench isolations is achieved. Dishing problems due to isolation oxide thinning over wide trenches is eliminated. A silicon substrate is provided. A pad oxide is grown. A polishing st... | 03/27/2001 |
| 6203408 | Variable pressure plate CMP carrier An apparatus for removably positioning a semiconductor wafer for polishing. The apparatus including a rotating member with a major lower surface having a plurality of recesses each with a conduit path radially leading to a smaller circular pattern of port... | 03/20/2001 |
| 6184104 | Alignment mark strategy for oxide CMP A method for generating alignment marks on the scribe lines in which alignment marks are generated only at oxide layers is described. An alignment mark is formed in an oxide layer on a scribe line of a wafer. The alignment mark is lined with a metal layer... | 02/06/2001 |
| 6180501 | Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process This invention relates to the fabrication of integrated circuit devices and more particularly to a method for minimizing the localized mechanical stress problems that can occur when silicided polysilicon gates are used to fabricate narrow channel CMOS dev... | 01/30/2001 |
| 6156654 | Pulsed laser salicidation for fabrication of ultra-thin silicides in sub-quarter micron devices Methods are disclosed for forming ultra-thin (~300-Å), uniform and stoichiometric C54-titanium silicide with a Ti film thickness of 200-300 Å using pulsed laser salicidation. The invention achieves this by preferably step-scanning from die to die, acros... | 12/05/2000 |
| 6150260 | Sacrificial stop layer and endpoint for metal CMP A new method of metal plug metallization utilizing a sacrificial layer as a CMP stop to protect the oxide layer from damage during CMP is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer cove... | 11/21/2000 |
| 6143598 | Method of fabrication of low leakage capacitor A capacitor element of a semiconductor device used for high density semiconductor circuits is formed by the steps of forming the bottom plate of the capacitor, submitting the top of the bottom plate to plasma treatment in an oxidizing medium where nitroge... | 11/07/2000 |
| 6136710 | Chemical mechanical polishing apparatus with improved substrate carrier head and method of use An improved and new substrate carrier head for use in a CMP apparatus is described. The new substrate carrier head has a substrate retaining ring with embedded intersecting channels in the outer face. The embedded intersecting channels improve the circula... | 10/24/2000 |
| 6112947 | Adjustable tank overflow for fluid chemicals An apparatus for adjusting a measure of liquid for mixing with a second liquid which includes an adjustable overflow tube cooperating within a closed tank. The tank has a threaded top port and a sleeved bushing bottom port. The top and bottom ports are ax... | 09/05/2000 |
| 6100155 | Metal-oxide-metal capacitor for analog devices A method for fabricating a metal-oxide-metal capacitor is described. A first insulating layer is provided overlying a semiconductor substrate. A conducting line is formed on the surface of said first insulating layer to act as the node contact for the cap... | 08/08/2000 |
| 6096647 | Method to form CoSi2 on shallow junction by Si implantation A new method for forming a cobalt disilicide film on shallow junctions with reduced silicon consumption in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A cobalt layer ... | 08/01/2000 |
| 6096604 | Production of reversed flash memory device This invention relates to the new reversed flash memory device which has improved electrical performance, yield and reliability because of better control of the dielectric interfaces resulting from first making the poly 2 control gate within the silicon s... | 08/01/2000 |
| 6093613 | Method for making high gain lateral PNP and NPN bipolar transistor compatible with CMOS for making BICMOS circuits A method and lateral bipolar transistor structure are achieved, with high current gain, compatible with CMOS processing to form BiCMOS circuits. Making a lateral PNP bipolar involves forming an N- well in a P- doped silicon substrate... | 07/25/2000 |
| 6093602 | Method to form polycide local interconnects between narrowly-spaced features while eliminating stringers A method of fabricating local interconnects of polycide has been achieved. A substrate is provided. Narrowly spaced features, such as MOS transistor gates and polysilicon traces, are provided overlying the substrate. A dielectric layer is deposited overly... | 07/25/2000 |
| 6071793 | Locos mask for suppression of narrow space field oxide thinning and oxide punch through effect A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field iso... | 06/06/2000 |
| 6069069 | Method for planarizing a low dielectric constant spin-on polymer using nitride etch stop A method for preserving the integrity of the underlying metal lines during planarization by inserting a nitride layer as an etch stop in an oxide-nitride-oxide dielectric layer underlying a spin-on polymer is described. Semiconductor device structures are... | 05/30/2000 |
| 6051467 | Method to fabricate a large planar area ONO interpoly dielectric in flash device A new method of fabricating a stacked gate Flash EEPROM device having an improved interpoly oxide layer is described. A gate oxide layer is provided on the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate oxi... | 04/18/2000 |
