Did You Know...
...that it was melting ice cream that inspired the invention of the outboard motor? It was a lovely August day and Ole Evinrude was rowing his boat to his favorite island picnic spot. As he rowed, he watched his ice cream melt and wished he had a faster way to get to the island. At that moment the idea for the outboard motor was born!
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6583045 | Chip design with power rails under transistors A method and an integrated circuit having power rails under transistors. In a preferred embodiment, power rails are formed over a substrate. Devices, such as FET transistors, are formed over the power rails. A preferred device is an inverter. The method c... | 06/24/2003 |
| 6556377 | Stitched write head design having a sunken shared pole A structure and a method for a stitched write head having a sunken share pole. The method includes forming a bottom coil dielectric layer over the first half shared pole. Coils are formed over the bottom coil dielectric layer. Next, second half shared pol... | 04/29/2003 |
| 6507090 | Fully silicide cascaded linked electrostatic discharge protection A method and a structure of for an Electro Static Discharge (ESD) device that is silicided. There are three preferred embodiments of the invention. The first embodiment has a N/P/N structure. The emitter, the collector and the substrate form a parasitic t... | 01/14/2003 |
| 6495446 | Lossless microstrip line in CMOS process A method and structure for a device with a signal line over a semiconductor structure where the signal line is formed over the ground plane, passivation layer, and polyimide layer. We provide a semiconductor structure comprising a substrate having devices... | 12/17/2002 |
| 6492205 | Utilization of macro power routing area for buffer insertion A structure and a method for forming cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the ... | 12/10/2002 |
| 6468870 | Method of fabricating a LDMOS transistor A method of manufacturing a LDHOS transistor having a dielectric block under the gate electrode. A high voltage well, low voltage well (LV PW), and field oxide regions having bird beaks are provided in a substrate and overlay the high voltage well and the... | 10/22/2002 |
| 6465367 | Lossless co-planar wave guide in CMOS process A structure and method of manufacturing a CMOS device where the Coplanar wave guide (CPW) lines are formed above the top metal lines. Also other insulating layers are provided that reduce the e-field from the signal line to the substrate. There are four e... | 10/15/2002 |
| 6458689 | Use of PE-SiON or PE-Oxide for contact or via photo and for defect reduction with oxide and w chemical-mechanical polish A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a dielectric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in... | 10/01/2002 |
| 6448649 | Multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnect The present invention provides a structure and a method of electrically connecting wiring layers by forming a stacked plug interconnect. The first wiring layer is formed over a dielectric layer and a top barrier layer is formed over the top of the first w... | 09/10/2002 |
| 6444510 | Low triggering N MOS transistor for ESD protection working under fully silicided process without silicide blocks An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+/n-/p-/n-/n+ regions. The emitter is formed of the second N+ region and the second N- well. The... | 09/03/2002 |
| 6436816 | Method of electroless plating copper on nitride barrier A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require ac... | 08/20/2002 |
| 6432588 | Method of forming an improved attenuated phase-shifting photomask A method of fabricating an attenuating phase-shifting photomask, comprising the following steps. A photomask blank is provided having an upper resist layer overlying a chromium layer, the chromium layer overlying a phase-shifting layer, and the phase-shif... | 08/13/2002 |
| 6413885 | Method for patterning semiconductor devices on a silicon substrate using oxynitride film A method for fabricating and patterning semiconductor devices with a resolution down to 0.12 μm on a substrate structure. The method begins by providing a substrate structure comprising various layers of oxide and/or nitride formed over either monocrysta... | 07/02/2002 |
| 6410403 | Method for planarizing a shallow trench isolation A method of planarizing an isolation region. Key elements of the invention include the two chemical-mechanical polish (CMP) steps and the CMP stop structure comprised of a sacrificial oxide layer and the second nitride layer. First a pad oxide layer, a fi... | 06/25/2002 |
| 6406743 | Nickel-silicide formation by electroless Ni deposition on polysilicon The present invention provides a method of manufacturing a nickel-silicide technology for polysilicon interconnects. Nickel 40 is deposited on polysilicon 30 using a electroless process. Using a rapid thermal anneal process, Ni 40 is transformed to NiSi a... | 06/18/2002 |
| 6399509 | Defects reduction for a metal etcher A method of patterning a metal line and removing the polymer layer that forms on the metal lines sidewalls in an important post etch-polymer removal step (e.g., step 4). A semiconductor structure and an overlying dielectric layer, a first barrier layer, a... | 06/04/2002 |
| 6379849 | Method for forming binary intensity masks A method for forming a binary intensity mask (BIM) using two writing steps. The first writing step has a narrow writing area, preferably about 1 micron, and outlines the desired pattern. The second writing area partially overlaps the first writing area, p... | 04/30/2002 |
| 6376351 | High Fmax RF MOSFET with embedded stack gate A method for forming a wide gate stack over a gate in a rf device is described. The invention reduces the gate resistance and the Rs significantly. A substrate has a digital area and a rf area. Devices used in digital circuits will be formed in the digita... | 04/23/2002 |
| 6372642 | Method for patterning semiconductor devices with a resolution down to 0.12 μm on a silicon substrate using oxynitride film and deep UV lithography A method for fabricating and patterning semiconductor devices with a resolution down to 0.12 μm on a substrate structure. The method begins by providing a substrate structure comprising various layers of oxide and/or nitride formed over either monocrysta... | 04/16/2002 |
| 6361904 | Method for repairing the shifter layer of an alternating phase shift mask A method for repairing shifter layer defects in a phase shifting mask. A two step process is used to form an equivalent shifter layer with about the same light transmittance and phase angle shift as an original, non-defective shifter layer. (Typically for... | 03/26/2002 |
| 6359336 | Boat and assembly method for ball grid array packages The present invention provides a boat and method for holding one or more substrates during a ball grid array packaging assembly. The boat comprises a base and one or more spring locks. The base has one or more openings which provide access to both faces o... | 03/19/2002 |
| 6348389 | Method of forming and etching a resist protect oxide layer including end-point etch The present invention provides a method for forming and etching a resist protect oxide layer, of which provides improved etch selectivity to a shallow trench isolation and an increased pre-metal dip processing window. The process begins by forming a shall... | 02/19/2002 |
| 6346449 | Non-distort spacer profile during subsequent processing A method for fabricating a junction for a field effect transistor which does not cause distortion of the sidewall spacers during subsequent processing thereby reducing junction depletion and source to drain leakage. The process begins by providing a subst... | 02/12/2002 |
| 6316348 | High selectivity Si-rich SiON etch-stop layer The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structu... | 11/13/2001 |
| 6309964 | Method for forming a copper damascene structure over tungsten plugs with improved adhesion, oxidation resistance, and diffusion barrier properties using nitridation of the tungsten plug A method for forming a damascene structure over tungsten plugs using nitridation of said tungsten plugs to provide better oxidation resistance, better adhesion properties and better copper diffusion barrier proerties. The process begins by providing a sub... | 10/30/2001 |
| 6303454 | Process for a snap-back flash EEPROM cell The present invention provides method to fabricate a snap-back flash EEPROMS device. The method begins by forming a gate structure 22 24 28 26 on a substrate. The gate structure comprises: a tunnel oxide layer 22, a floating gate 24, integrate dielectric ... | 10/16/2001 |
| 6297102 | Method of forming a surface implant region on a ROM cell using a PLDD implant The invention provides a method for forming a ROM cell surface implant region using a PLDD implant. A semiconductor structure is provided comprising a substrate having isolation structures thereon, which separate and electrically isolating a first area ha... | 10/02/2001 |
| 6287476 | Electrochemical method to improve MR reader edge definition and device reliability A method to form a passivation layer using an electrochemical process over a MR Sensor so that the passivation layer defines the MR track width. The passivation layer is formed by anodizing the MR sensor. The passivation layer is an electrical insulator (... | 09/11/2001 |
| 6287939 | Method for fabricating a shallow trench isolation which is not susceptible to buried contact trench formation The invention provides a method for fabricating a shallow trench isolation which is not susceptable to buried contact trench formation. The invention also provides immunity from the STI "kink effect," as well as benefits associated with nitridation. The p... | 09/11/2001 |
| 6284611 | Method for salicide process using a titanium nitride barrier layer This invention provides a method for forming a self-aligned silicide with low sheet resistance in the N+ source and drain regions and the N+ polysilicon regions in a semiconductor device using a titanium nitride barrier layer to prevent nitridation of an ... | 09/04/2001 |
| 6284107 | Method for controlling arcing across thin dielectric film A method for preventing and controlling Arcing Across Thin Dielectric Film in sputtering and other process that generate electric fields and cause arcing across conductive structures. In a first embodiment, when the wafer is subjected to RF electric field... | 09/04/2001 |
| 6284572 | Boat and assembly method for ball grid array packages The present invention provides a boat and method for holding one or more substrates during a ball grid array packaging assembly. The boat comprises a base and one or more spring locks. The base has one or more openings which provide access to both faces o... | 09/04/2001 |
| 6277528 | Method to change transmittance of attenuated phase-shifting masks A method of forming a high transmittance attenuated phase-shifting mask blank, comprising the following steps. An attenuated phase-shifting mask is provided that includes a shifter layer overlying a transparent substrate. The attenuated phase-shifting mas... | 08/21/2001 |
| 6277719 | Method for fabricating a low resistance Poly-Si/metal gate A method for forming a low resistance metal/polysilicon gate for use in CMOS devices comprising: (1) a novel anneal step prior to formation of a diffusion barrier layer and (2) a novel diffusion barrier layer composed of titanium nitride deposited over ti... | 08/21/2001 |
| 6274025 | Chemical approach to develop lift-off photoresist structure and passivate MR sensor A method to form a passivation layer over a MR Sensor so that the passivation layer defines the track width. The passivation layer is formed simultaneously with the development of the lift off structure in a novel developing/oxidizing solution that oxidiz... | 08/14/2001 |
| 6271123 | Chemical-mechanical polish method using an undoped silicon glass stop layer for polishing BPSG A method using chemical-mechanical polishing for planarizing a BPSG layer 30 using a overlying Undoped Silicate Glass (USG) cap layer 40 comprising: (a) form a BPSG layer 30 over the semiconductor structure 12; the BPSG layer 30 over the periphery area 16 havi... | 08/07/2001 |
| 6271117 | Process for a nail shaped landing pad plug The invention has two embodiments for forming a contact plug having large nail shaped landing pad. The large pad areas increase the overlay tolerances. The first embodiment comprises forming first 20 and second 24 insulating layers over a semiconductor st... | 08/07/2001 |
| 6258734 | Method for patterning semiconductor devices on a silicon substrate using oxynitride film A method for fabricating and patterning semiconductor devices with a resolution down to 0.12 μm on a substrate structure. The method begins by providing a substrate structure comprising various layers of oxide and/or nitride formed over either monocrysta... | 07/10/2001 |
| 6255715 | Fuse window guard ring structure for nitride capped self aligned contact processes The present invention provides a structure and method for forming a moisture barrier guard ring structure 38 44 48 52 54 for around a fuse window 30 in a semiconductor device. The invention begins by forming a fuse structure 32 33 34 over the isolation re... | 07/03/2001 |
| 6251724 | Method to increase the clear ration of capacitor silicon nitride to improve the threshold voltage uniformity A method to remove the silicon nitride capacitor dielectric layer from over the poly-1 layer on portions of the wafer including non-capacitor areas such as the pad contact area, process control monitor (PCM) testsite areas and scribe line areas. By removi... | 06/26/2001 |
