Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 6606782 | Method of forming a continuous free layer spin valve sensor with patterned exchange underlayer stabilization To form a spin valve device, start by forming a gap layer. Form a buffer layer with a layer of refractory material on the buffer layer. Form patterned underlayers including a magnetic material for providing trackwidth and longitudinal bias on the buffer l... | 08/19/2003 |
| 6600228 | Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule A planarized surface of a photoresist layer is formed above a layer formed over a hole in a blanket, conformal, silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor d... | 07/29/2003 |
| 6583466 | Vertical split gate flash memory device in an orthogonal array of rows and columns with devices in columns having shared source regions A vertical transistor memory device includes FET cells formed in rows and columns with the rows orthogonally arranged relative to the columns. Several cells in a single row have a common source region and adjacent cells have a common drain region FOX regi... | 06/24/2003 |
| 6576384 | Mask image scanning exposure method A dynamic mask exposure method and system includes a support for a workpiece, a source of a beam of exposure radiation, and a transmissive dynamic mask with orthogonally arranged matrices of actuator lines and binary pixel units which are opaque or transp... | 06/10/2003 |
| 6555433 | Method of manufacture of a crown or stack capacitor with a monolithic fin structure made with a different oxide etching rate in hydrogen fluoride vapor In this process, a capacitor core is formed on a semiconductor device with a first conductive sublayer in contact with a plug. First form a stack of alternately doped and undoped oxide layers on the sublayer with the stack comprising a bottom layer formed... | 04/29/2003 |
| 6548856 | Vertical stacked gate flash memory device A method of forming a vertical transistor memory device comprises the following process steps. Before forming the trenches, FOX regions are formed between the rows. Then form a set of trenches with sidewalls and a bottom in a semiconductor substrate with ... | 04/15/2003 |
| 6514839 | ESD implantation method in deep-submicron CMOS technology for high-voltage-tolerant applications with light-doping concentrations An implanting method forms high-voltage-tolerant ESD protection devices (ESDPD) for deep-submicron CMOS process activated between LDD implanting and forming sidewall spacers. ESD-Implant (ESDI) regions are located at the ESDPD, without covering the center... | 02/04/2003 |
| 6509603 | P-channel EEPROM and flash EEPROM devices A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilic... | 01/21/2003 |
| 6483159 | Undoped polysilicon as the floating-gate of a split-gate flash cell A split gate EEPROM memory device formed on a doped silicon semi-conductor substrate starting with an initial oxide layer with an undoped first polysilicon layer formed thereon. A polysilicon oxide hard mask over the undoped first polysilicon layer for us... | 11/19/2002 |
| 6480794 | Method for minimizing total test time for testing factories To allocate products for machines on a manufacturing line, provide a standard test time. Minimize total test time with respect to production scheduling. Form a supply demand matrix table for products and machines for product allocation. Find the grid loca... | 11/12/2002 |
| 6477432 | Statistical in-process quality control sampling based on product stability through a systematic operation system and method A system for managing quality control in a manufacturing plant for processing lots of work in process (WIP) for at least one product, comprises a manufacturing process which includes a manufacturing executive system (MES) which provides inspection data to... | 11/05/2002 |
| 6476460 | Stacked gate MOS structure for multiple voltage power supply applications A capacitor structure is formed on a semiconductor substrate to provide split voltages for semiconductor circuits. An active area is formed in the substrate serving as a lower capacitor plate for a bottom capacitor. A thin dielectric layer and field oxide... | 11/05/2002 |
| 6455887 | Nonvolatile devices with P-channel EEPROM device as injector An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in... | 09/24/2002 |
| 6429142 | In-situ photoresist removal by an attachable chamber with light source A method of fabricating integrated circuit wafers, in accordance with this invention comprises the following steps. Provide an integrated circuit wafer having devices formed therein covered with a metal layer and a photoresist layer over the metal layer w... | 08/06/2002 |
| 6430015 | Method of fabrication of striped magnetoresistive (SMR) and dual stripe magnetoresistive (DSMR) heads with anti-parallel exchange configuration A longitudinally magnetically biased dual stripe magnetoresistive (DSMR) sensor element comprises a first patterned magnetoresistive (MR) layer. There are contacts at the opposite ends of the patterned magnetoresistive (MR) layer with a first pair of stac... | 08/06/2002 |
| 6397373 | Efficient design rule check (DRC) review system A method/system is provided for performing a design review checking operation and analyzing the resultant data. Perform a DRC operation describing chip features and generating flags for violation sites including patterns and paths. Execute pattern analysi... | 05/28/2002 |
| 6393692 | Method of manufacture of a composite shared pole design for magnetoresistive merged heads A merged read/write magnetic recording head comprises a low magnetic moment first magnetic shield layer over a substrate. A read gap layer with a magnetoresistive head is formed over the first shield layer. A shared pole comprises a low magnetic moment se... | 05/28/2002 |
| 6391719 | Method of manufacture of vertical split gate flash memory device A method of forming a vertical transistor memory device includes the following steps. Before forming the trenches, FOX regions are formed between the rows. Form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold impl... | 05/21/2002 |
| 6389323 | Method and system for yield loss analysis by yield management system A method and system provide for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages. The method comprising the following steps. Inspect semiconductor devices on the... | 05/14/2002 |
| 6385017 | Continuous free layer spin valve sensor with patterned exchange underlayer stabilization A spin valve device comprises a free layer, a spacer layer, a pinned layer, an antiferromagnetic layer, and a patterned underlayer that includes a magnetic material for providing trackwidth and longitudinal bias. The patterned underlayer can comprise a bu... | 05/07/2002 |
| 6355962 | CMOS FET with P-well with P- type halo under drain and counterdoped N- halo under source region A semiconductor device is formed on a semiconductor substrate with an N-well and a P-well with source/drain sites in the N-well and in the P-well by the following steps. Form a gate oxide layer and a gate electrode layer patterned into a gate electrode st... | 03/12/2002 |
| 6353769 | Method for allocating lot priority by ranking lots as a function of budget queue time in a manufacturing control system A system and a method are provided employing the concept of Budget Queue Time to define the priority of lots while distinguishing clearly between the controllable an uncontrollable portions of the remaining production time needed and to make the priority ... | 03/05/2002 |
| 6353260 | Effective diffusion barrier In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole on the bottom in the dielectric layer with the overall tr... | 03/05/2002 |
| 6344392 | Methods of manufacture of crown or stack capacitor with a monolithic fin structure made with a different oxide etching rate in hydrogen fluoride vapor A capacitor core is formed on a semiconductor device with a first conductive layer in contact with a plug. A mold is formed from a stack of alternately doped and undoped silicon dioxide layers on the sublayer with the stack comprising a bottom layer forme... | 02/05/2002 |
| 6326662 | Split gate flash memory device with source line A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate el... | 12/04/2001 |
| 6324037 | Magnetically stable spin-valve sensor A laminated spin-valve sensor comprises a fixed magnetic layer and a free-layer separated by a thin spacer layer, with electrical leads interconnected to ends of the sensor. The sensor is longitudinally biased by permanently magnetized structures between ... | 11/27/2001 |
| 6310397 | Butted contact resistance of an SRAM by double VCC implantation Form a butted contact in an SRAM memory device by exposing a contact region on the surface of a doped semiconductor substrate and a conductor stack above a field oxide region on the surface of the substrate. Form an interpolysilicon silicon oxide dielectr... | 10/30/2001 |
| 6294456 | Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule This is a method of planarizing a surface of a photoresist layer formed above a layer formed over a gap in a blanket silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconduc... | 09/25/2001 |
| 6281545 | Multi-level, split-gate, flash memory cell A semiconductor memory device is formed on a doped semiconductor substrate, and covered with a tunnel oxide layer covered in turn with a doped first polysilicon layer. The first polysilicon layer is patterned into a pair of floating gate electrodes. An in... | 08/28/2001 |
| 6265249 | Method of manufacturing thin film transistors An additional high quality insulating layer is grown over the substrate after the formation of the gate electrode of a thin film transistor (TFT). The growth temperature of the insulating layer can be higher than conventional method and the insulating lay... | 07/24/2001 |
| 6266144 | Stepper and scanner new exposure sequence with intra-field correction A method and system are provided for determining the degree of overlay misregistration when exposing a semiconductor wafer having a center and a periphery comprises the following steps. Expose the wafer with a scan in a sequence from the center of the waf... | 07/24/2001 |
| 6255734 | Passivated copper line semiconductor device structure A method of forming a copper conductor for a thin film electronic device comprises: forming layers over a conductor into a stack of barrier layer superjacent on top of the substrate, a copper layer on top of the barrier layer, and a hard mask layer on top... | 07/03/2001 |
| 6221758 | Effective diffusion barrier process and device manufactured thereby In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole on the bottom in the dielectric layer with the overall tr... | 04/24/2001 |
| 6215578 | Electronically switchable off-axis illumination blade for stepper illumination system An off axis illumination stepper exposure system includes an illumination system with an aperture element and lenses. The aperture element comprises an array of electronically switchable pixels in a matrix. The aperture element can be a transmissive spati... | 04/10/2001 |
| 6207503 | Method for shrinking array dimensions of split gate flash memory device using multilayer etching to define cell and source line A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate el... | 03/27/2001 |
| 6204071 | Method of fabrication of striped magnetoresistive (SMR) and dual stripe magnetoresistive (DSMR) heads with anti-parallel exchange configuration A method for forming a longitudinally magnetically biased dual stripe magnetoresistive (DSMR) sensor element comprises forming a first patterned magnetoresistive (MR) layer. Contact the opposite ends of the patterned magnetoresistive (MR) layer with a fir... | 03/20/2001 |
| 6198173 | SRAM with improved Beta ratio A method of forming an SRAM transistor cell on a doped semiconductor substrate with a halo region in transistors thereof by the steps including well formation, field isolation formation, threshold voltage implant, gate oxidation; deposition of polysilicon... | 03/06/2001 |
| 6181013 | Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls ... | 01/30/2001 |
| 6174767 | Method of fabrication of capacitor and bit-line at same level for 8F2 DRAM cell with minimum bit-line coupling noise A structure with bit lines and capacitors for a semiconductor memory device is formed by the following steps. Form a gate oxide layer on a doped silicon semiconductor substrate. Form gate electrode stacks juxtaposed with conductive plugs over the gate oxi... | 01/16/2001 |
| 6172395 | Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby A method of manufacture of self-aligned floating gate, flash memory device on a semiconductor substrate includes the following steps. Form a blanket silicon oxide layer over the substrate. Form a blanket floating gate conductor layer over the silicon oxid... | 01/09/2001 |
