Quotables
"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Number | Title | Issue Date |
| 6687103 | Charge/discharge protection circuit The invention refers to a charge/discharge protection circuit for a rechargeable battery, where the protection circuit is integrated on a single chip, including the fusible link, the load current switch and the short-circuit switch. This is achieved by di... | 02/03/2004 |
| 6687563 | Integration method of dispatch and schedule tools for 300 mm full automation Fab A method and system that creates a rule-based Operation Job Supervisor System (OJS) or decision engine to automate and control Fab production for the optimum movement of wafer boxes through the Fab. It is integrated with current manufacturing control syst... | 02/03/2004 |
| 6686280 | Sidewall coverage for copper damascene filling A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First... | 02/03/2004 |
| 6607942 | Method of fabricating as grooved heat spreader for stress reduction in an IC package A new design is provided for the heat spreader of a semiconductor package. Grooves are provided in a surface of the heat spreader, subdividing the heat spreader for purposes of stress distribution into four or more sections. This division of the heat spre... | 08/19/2003 |
| 6608737 | Method to make a stitched writer for a giant magneto-resistive head A giant magneto-resistive head is provided which includes a novel high data-rate stitched pole inductive magnetic write head. The write head incorporates a non-magnetic spacer layer and a magnetic pole yoke that is recessed from the magnetic pole tip. The... | 08/19/2003 |
| 6606263 | Non-disturbing programming scheme for magnetic RAM In magnetic RAMs a particular memory cell is selected when it is at the intersection of a row and a column of half-selected cells. When data is written into the selected cell, the associated magnetic field can sometimes disturb a neighboring half-selected... | 08/12/2003 |
| 6605973 | High voltage discharge circuit This invention provides a circuit and a method for discharging a high voltage to ground level from a circuit node especially in intergrated circuits. The invention relates to a high voltage discharge circuit which prevents semiconductor latch-up and preve... | 08/12/2003 |
| 6605528 | Post passivation metal scheme for high-performance integrated circuit devices A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick ... | 08/12/2003 |
| 6605524 | Bumping process to increase bump height and to create a more robust bump structure A new process is provided which is an extension and improvement of present processing for the creation of a solder bump. After the layers of Under Bump Metal and a layer of solder metal have been created in patterned and etched format and overlying the co... | 08/12/2003 |
| 6605493 | Silicon controlled rectifier ESD structures with trench isolation A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates polysilicon gates bridging SCR diode junction elements and also bridging between SCR elements and... | 08/12/2003 |
| 6605535 | Method of filling trenches using vapor-liquid-solid mechanism A method of filling trenches such as a DT cell with silicon is described that involves a vapor-liquid-solid (VLS) mechanism. First, a thin film of Si is grown on the trench sidewalls. Seed metal such as Au, Ni or Ni alloy is deposited on the sidewalls by ... | 08/12/2003 |
| 6602641 | Wafer's zero-layer and alignment mark print without mask when using scanner A new method is provided for the use of alignment marks. In prior art methods, a combination mask is mounted in a mask holder. The combination mask contains multiple, different alignment marks for different purposes and steps in a semiconductor processing... | 08/05/2003 |
| 6598314 | Method of drying wafers A new method and apparatus is provided for the cleaning and drying of a wafer. An IPA vapor is created using an ultrasonic nebulizer that can be operated at a relatively low temperature. The water and the IPA that is used by the cleaning and drying proces... | 07/29/2003 |
| 6599847 | Sandwich composite dielectric layer yielding improved integrated circuit device reliability A method for forming for use within an integrated circuit a gap filling sandwich composite dielectric layer construction, and an integrated circuit having formed therein the gap filling sandwich composite dielectric layer construction. To practice the met... | 07/29/2003 |
| 6599779 | PBGA substrate for anchoring heat sink In accordance with the objectives of the invention a new method is provided to position and secure a heat sink over the surface of a semiconductor device mounting support, the latter typically being referred to as a semiconductor substrate. A plurality of... | 07/29/2003 |
| 6600594 | Intelligent variable optical attenuator with controller and attenuation calibration A variable optical attenuation system has at least one variable optical attenuation device that receives a light signal, attenuates the light signal, and transmits an attenuated light signal. The variable optical attenuator system further has a controller... | 07/29/2003 |
| 6600357 | High voltage level shifter According to the present invention, a voltage level shifter with smaller size and less latch-up probability is described, in which extra two N-MOS transistors and two P-MOS transistors are added. The extra transistors help node voltages increase or decrea... | 07/29/2003 |
| 6596619 | Method for fabricating an under bump metallization structure An under bump metallurgy (UBM) structure is described. Two UBM mask processes are utilized. First, a top layer of copper (Cu) and/or a middle layer of nickel-vanadium (NiV) or chrome-copper (CrCu) is personalized by standard photoprocessing and etching st... | 07/22/2003 |
| 6596599 | Gate stack for high performance sub-micron CMOS devices A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the ga... | 07/22/2003 |
| 6596468 | Process to form a flux concentration stitched write head A general process for filling a trench is described with particular emphasis on the formation of step P1 during the manufacture of a magnetic write head. The main feature of this process is that a liftoff mask is used for both the trench formation and the... | 07/22/2003 |
| 6597188 | Ground land for singulated ball grid array A new ground land is provided on the BGA package that allows for increasing the test sensitivity of a wire bond tester. The ground land is interconnected with a ground ring that is provided in the immediate vicinity of the BGA device. The ground land of t... | 07/22/2003 |
| 6591480 | Process for fabricating a flux concentrating stitched head A method for fabricating a flux concentrating stitched write head for high data rate applications wherein said flux concentration is achieved by means of a non-magnetic step embedded into a portion of the lower magnetic pole just beneath the write gap lay... | 07/15/2003 |
| 6594124 | Canted adjacent layer stabilized SV heads An improved stabilization scheme for a GMR read head is described. Two important changes relative to prior art designs have been introduced. Instead of biasing by means of a permanent magnet or through exchange coupling with an antiferromagnetic layer, th... | 07/15/2003 |
| 6593649 | Methods of IC rerouting option for multiple package system applications A new method is provided for the creation of Input/Output connection points to a semiconductor device package. An extension is applied to the conventional I/O connect points of a semiconductor device, allowing the original I/O point location to be relocat... | 07/15/2003 |
| 6593220 | Elastomer plating mask sealed wafer level package method A new method is provided for the creation of a solder mask for solder bump formation. A passivation layer is deposited on the semiconductor surface in the surface of which a contact pad has been provided, an opening is created in the layer of passivation ... | 07/15/2003 |
| 6592019 | Pillar connections for semiconductor chips and method of manufacture A flip chip interconnect system comprises an elongated pillar comprising two elongated portions, a first portion including solder with or without lead and a second portion including copper or gold or other material having a higher reflow temperature than ... | 07/15/2003 |
| 6589836 | One step dual salicide formation for ultra shallow junction applications A process for formation of metal silicide on elements of an NMOS device and on elements of a PMOS device, wherein the metal silicide formed on elements of the PMOS device is thinner than the metal silicide simultaneously formed on elements of said NMOS de... | 07/08/2003 |
| 6590751 | Anisotropic magnetoresistive (MR) sensor element with enhanced magnetoresistive (MR) coefficient A method for forming an anisotropic magnetoresistive (MR) sensor element, and the anisotropic magnetoresistive (MR) sensor element formed in accord with the method. In accord with the method, there is first provided a substrate. There is then formed over ... | 07/08/2003 |
| 6590262 | High voltage ESD protection device with very low snapback voltage A device layout is disclosed for an ESD device for protecting NMOS high voltage transistors where the SCR protection device and the two NMOS transistors are integrated. The two NMOS transistors share an n-type doped drain (ndd) area which has implanted tw... | 07/08/2003 |
| 6589872 | Use of low-high slurry flow to eliminate copper line damages The invention teaches a new method of applying slurry during the process of chemical mechanical polishing of copper surfaces. By varying the rate of slurry deposition, starting out with a low rate of slurry flow that is increased as the polishing process ... | 07/08/2003 |
| 6586331 | Low sheet resistance of titanium salicide process A method for establishing low sheet resistance for the Titanium Salicide process that teaches a C-54 TiSix process by means of an additional vacuum bake. The present invention teaches an additional vacuum bake step prior to pre-metal HF dip dur... | 07/01/2003 |
| 6586925 | Method and apparatus for establishing quick and reliable connection between a semiconductor device handler plate and a semiconductor device test head plate A new method and apparatus is provided to quickly and reliably position, connect and dock a handler plate with a test head plate of a Universal Docking System. A handler plate is provided with roller assemblies while a test head plate is provided with mat... | 07/01/2003 |
| 6586846 | Low cost decal material used for packaging A new method is provided for mounting high-density IC semiconductor devices. A layer of epoxy is deposited over the first surface of a metal panel. One or more thin film interconnect layers are then created on top of the epoxy layer. The BUM technology al... | 07/01/2003 |
| 6586142 | Method to overcome image distortion of lines and contact holes in optical lithography A process to correct distortions due to optical proximity effects is described. A two reticle per pattern approach is used. The first, or primary, reticle contains the image that is to be transferred to the photoresist. It is used to expose the resist in ... | 07/01/2003 |
| 6586323 | Method for dual-layer polyimide processing on bumping technology A new method and processing sequence is provided for the formation of solder bumps that are in contact with underlying aluminum contact pads. A patterned layer of negative photoresist is interposed between a patterned layer of PE Si3 N4 | 07/01/2003 |
| 6586765 | Wafer-level antenna effect detection pattern for VLSI A test structure for evaluating plasma damage in thin gate oxides is formed with a single polysilicon floating gate EEPROM device on which an antenna structure delivers charge to a floating gate through a tunnel oxide. The floating gate extends beyond the... | 07/01/2003 |
| 6586347 | Method and structure to improve the reliability of multilayer structures of FSG (F-doped SiO2) dielectric layers and metal layers in semiconductor integrated circuits An improved composite dielectric structure and method of forming thereof which prevents delamination of FSG (F-doped SiO2) and allows FSG to be used as the interlevel dielectric between successive conducting interconnection patterns in multilev... | 07/01/2003 |
| 6584034 | Flash memory array structure suitable for multiple simultaneous operations In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plur... | 06/24/2003 |
| 6583966 | Method to make a high data rate stitched writer for a giant magneto-resistive head A high data-rate stitched pole magnetic read/write-head combining sputtered and plated high magnetic moment materials and a method for fabricating same. The plating and stitching aspects of this fabrication allow the formation of a very narrow write-head,... | 06/24/2003 |
| 6582988 | Method for forming micro lens structures The present invention features a method for forming micro lens arrays on light-sensitive or light-emitting semiconductor structures. A unique oxygen plasma etch "descum" step is performed prior to the lens reflow hardbake. In addition, a photo-sensitive p... | 06/24/2003 |
