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| Number | Title | Issue Date |
| 7153766 | Metal barrier cap fabrication by polymer lift-off A new method is provided for the creation of copper interconnects. A pattern of copper interconnects is created, a protective layer of semiconductor material is deposited over the surface of the created copper interconnects. The protective layer is patterned and etc... | 12/26/2006 |
| 7064538 | Magnetic sensor digital processing interface for electrical motor application A system and methods for an interface for magnetic sensors to determine a rotational angle has been achieved. This interface can be used for magnetic sensors providing analog signals of the sine and cosine values of the angle to be determined. Analog signals are bei... | 06/20/2006 |
| 7061730 | Robust hard bias/conductor lead structures for future GMR heads A spin-valve magnetoresistive read element has a thin conductive lead layer of high sheet conductivity, high hardness, high melting point, high corrosion resistance and lacking the propensity for smearing, oozing, electromigration and nodule formation. Said lead lay... | 06/13/2006 |
| 7061339 | Enhanced architectures of voltage-controlled oscillators with single inductor (VCO-1L) Methods to achieve low power consumption, high output amplitude and an improved high frequency stability, and high speed for voltage-controlled oscillators are disclosed These methods includes to provide a current mirror, a power supply voltage Vdd, two single-ended... | 06/13/2006 |
| 7050273 | Bottom spin valve sensor having a lead overlay (LOL) structure fabricated thereon A method for fabricating a longitudinally hard biased, bottom spin valve GMR sensor with a lead overlay (LOL) conducting lead configuration and a narrow effective trackwidth. The advantageous properties of the sensor are obtained by providing two novel barrier layer... | 05/23/2006 |
| 7045841 | Oxidation structure/method to fabricate a high-performance magnetic tunneling junction MRAM An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) has a tunneling barrier layer of substantially uniform and homogeneous Al2O3 stoichiometry. The barrier layer is formed by depositing Al on a CoFe layer or a CoFe—NiFe ... | 05/16/2006 |
| 7045901 | Chip-on-chip connection with second chip located in rectangular open window hole in printed circuit board A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window ... | 05/16/2006 |
| 7046556 | Twin insulator charge storage device operation and its fabrication method The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the pro... | 05/16/2006 |
| 7046999 | Half-duplex wireless audio communication system A wireless communication system that transmits content signals and remote control signals between a content retention and distribution system and a content reproduction terminal over a half-duplex channel such as an RF channel having the same frequency band. The wir... | 05/16/2006 |
| 7042682 | Fully shielded perpendicular recoding writer Conventional perpendicular writers that utilize an extended return pole are subject to large flux leakage. This problem has been reduced in the prior art by adding a downstream shield. This still leaves significant upstream leakage. This has now been eliminated by a... | 05/09/2006 |
| 7038550 | Smart current controlled (SCC) resonator driver A circuit and a method are given, to realize and implement an oscillator circuit with a Smart Current Controlled (SCC) Resonator Driver. A newly introduced controlled current source for a crystal oscillator's amplifier element produces a controlled driving current f... | 05/02/2006 |
| 7038880 | Method to make a planar writer with low D.C. coil resistance An inductive-type write head and its method of fabrication are disclosed. The write head has a vertically separated two-element planar coil of reduced resistance which is the result of forming the lower of the two coils with windings of a greater height and substant... | 05/02/2006 |
| 7039784 | Video distribution system using dynamic disk load balancing with variable sub-segmenting A method and apparatus for dynamically balancing the loading of video data storage devices facilitates the transfer of video data by acquiring a listing of locations and loading of all segments of a requested video data. Those storage devices containing copies of ea... | 05/02/2006 |
| 7034873 | Pixel defect correction in a CMOS active pixel image sensor Effectively defect free images are obtained from CMOS image sensors through a two step method in which the addresses of bad pixels are recorded during sensor testing and stored in an on-chip directory. Then, during sensor readout, each pixel address is checked to de... | 04/25/2006 |
| 7035060 | Easily manufactured exchange bias stabilization scheme A problem associated with current bottom spin valve designs is that it is difficult to avoid magnetic charge accumulation at the edge of the sensor area, making a coherent spin rotation during sensing difficult to achieve. This problem has been eliminated by introdu... | 04/25/2006 |
| 7029375 | Retaining ring structure for edge control during chemical-mechanical polishing The retaining ring has a plurality of slurry channels wherein each alternate channel is recessed away from the inner circumference of the pad contacting surface forming a recess which extends upward from the bottom surface sufficient to prevent contact of the retain... | 04/18/2006 |
| 7031192 | Non-volatile semiconductor memory and driving method A data control unit is used to proved program, erase and verify signals to a non-volatile metal-oxide3-nitride-oxide-semiconductor (MONOS) memory. The data control unit comprises a plurality of sub-units that each contains a sense amplifier, two bi-directional flip-... | 04/18/2006 |
| 7022625 | Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration A method of forming a silicon nitride-silicon dioxide, composite gate dielectric layer, offering reduced risk of boron penetration from an overlying boron doped polysilicon gate structure, has been developed. A porous, silicon rich silicon nitride layer is first dep... | 04/04/2006 |
| 7022383 | Exchange bias structure for abutted junction GMR sensor Although it is known that exchange bias can be utilized in abutted junctions for longitudinal stabilization, a relatively large moment is needed to pin down the sensor edges effectively. Due to the inverse dependence of the exchange bias on the magnetic layer thickn... | 04/04/2006 |
| 7023750 | Dynamical biasing of memory sense amplifiers A circuit and a method are given, to realize a dynamical biasing of memory sense amplifiers for Sense Electronics Endowed (SEE) memory devices. Fast memories uses sense amplifiers in the read path in order to react fast with the data being delivered from a given add... | 04/04/2006 |
| 7017758 | Wafer protective cassette A substrate cassette having a conventional form, an open container having an upper entrance and a narrow lower opening formed by two side panels and two end panels. A preferred embodiment includes a train of substrate alignment channels on the inner surfaces of the ... | 03/28/2006 |
| 7016168 | Method of increasing CPP GMR in a spin valve structure A current-perpendicular-to-plane (CPP) giant magnetoresistive (GMR) sensor of the synthetic spin valve type is provided, the sensor comprising a GMR stack having a substantially square lateral cross-section, a Cu spacer layer of smaller square cross-section formed c... | 03/21/2006 |
| 7012789 | Composite shared pole design for magnetoresistive merged heads A merged read/write magnetic recording head comprises a low magnetic moment first magnetic shield layer over a substrate. A read gap layer with a magnetoresistive head is formed over the first shield layer. A shared pole comprises a low magnetic moment second magnet... | 03/14/2006 |
| 7012022 | Self-patterning of photo-active dielectric materials for interconnect isolation In accordance with the objectives of the invention a new method is provided for the creation of an interconnect pattern. The invention provides for a layer of Photo-Active Dielectric (PAD) to be used for the insulation material in which the interconnect pattern is c... | 03/14/2006 |
| 7013288 | Methods and systems for managing the distribution of image capture devices, images, and prints The present invention is generally directed to methods and systems for distributing image capture devices, images, and prints. One embodiment of the present invention advantageously provides cameras, such as digital cameras or film cameras, to consumers for free or ... | 03/14/2006 |
| 7009429 | Method and circuit for compensating MOSFET capacitance variations in integrated circuits A method for tracking the MOS oxide thickness by the native threshold voltage of a “native” MOS transistor without channel implantation for the purpose of compensating MOS capacitance variations is achieved. The invention makes use of the fact that in MOS device... | 03/07/2006 |
| 7006046 | Low cost electronic probe devices manufactured from conductive loaded resin-based materials Electronic probe devices are formed of a conductive loaded resin-based material. The conductive loaded resin-based material comprises micron conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers in a base resin host. ... | 02/28/2006 |
| 7006050 | Low cost antennas manufactured from conductive loaded resin-based materials having a conducting wire center core Low cost moldable antennas and methods of forming the antennas are described. Elements of the antennas are conductive loaded resin-based material having a conducting wire center. The conducting wire center can be single strand, multi-strand, insulated, or non-insula... | 02/28/2006 |
| 7006378 | Array architecture and operation methods for a nonvolatile memory A nonvolatile memory device is achieved. The device comprises a string of MONOS cells connected drain to source. Each MONOS cell comprises a wordline gate overlying a channel region in a substrate. First and second control gates each overlying a channel region in th... | 02/28/2006 |
| 7006337 | Multilayered structures comprising magnetic nano-oxide layers for current perpendicular to plane GMR heads Nano-oxide based current-perpendicular-to-plane (CPP) magnetoresistive (MR) sensor stacks are provided, together with methods for forming such stacks. Such stacks have increased resistance and enhanced magnetoresistive properties relative to CPP stacks made entirely... | 02/28/2006 |
| 7002870 | Speeding up the power-up procedure for low power RAM An internal power system for a low power memory chip is described that provides a large capacity internal power source during chip power up and during an active state whereby memory operations are carried out. A memory chip standby state allows reduced chip power wh... | 02/21/2006 |
| 7002234 | Low cost capacitors manufactured from conductive loaded resin-based materials Capacitors are formed of a conductive loaded resin-based material. The conductive loaded resin-based material comprises micron conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers in a base resin host. The ratio of t... | 02/21/2006 |
| 7002175 | Method of making resonant tunneling diodes and CMOS backend-process-compatible three dimensional (3-D) integration A double barrier resonant tunneling diode (RTD) is formed and integrated with a level of CMOS/BJT/SiGe devices and circuits through processes such as metal-to-metal thermocompressional bonding, anodic bonding, eutectic bonding, plasma bonding, silicon-to-silicon bon... | 02/21/2006 |
| 7002421 | Method and circuit for compensating MOSFET capacitance variations in integrated circuits A method for tracking the MOS oxide thickness by the native threshold voltage of a “native” MOS transistor without channel implantation for the purpose of compensating MOS capacitance variations is achieved. The invention makes use of the fact that in MOS device... | 02/21/2006 |
| 6999345 | Method of sense and program verify without a reference cell for non-volatile semiconductor memory A method and circuit for verify and read of a nonvolatile memory cell without the use of a reference cell is described. The circuit comprises a sense amplifier that compares a voltage from the output of a read path of a selected bit line to a reference voltage. When... | 02/14/2006 |
| 6998685 | Electrostatic discharge protection device with complementary dual drain implant Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the ... | 02/14/2006 |
| 6998682 | Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific location... | 02/14/2006 |
| 6998150 | Method of adjusting CoFe free layer magnetostriction It has been found that the insertion of a copper laminate within CoFe, or a CoFe/NiFe composite, leads to higher values of CPP GMR and DRA. However, this type of structure exhibits very negative magnetostriction, in the range of high −10−6 to −10 | 02/14/2006 |
| 6998953 | High performance RF inductors and transformers using bonding technique A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurality of wire ... | 02/14/2006 |
| 6995959 | Integrated spin valve head Currently, the shield-to-shield separation of a spin valve head cannot be below about 800 Å, mainly due to sensor-to-lead shorting problems. This problem has now been overcome by inserting a high permeability, high resistivity, thin film shield on the top or botto... | 02/07/2006 |
