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Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
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| Number | Title | Issue Date |
| 8183642 | Gate effective-workfunction modification for CMOS CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control lay... | 05/22/2012 |
| 8178430 | N-type carrier enhancement in semiconductors A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implan... | 05/15/2012 |
| 8138543 | Hybrid FinFET/planar SOI FETs A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the pla... | 03/20/2012 |
| 8122400 | Logic difference synthesis A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original... | 02/21/2012 |
| 8030716 | Self-aligned CMOS structure with dual workfunction A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blan... | 10/04/2011 |
| 8003455 | Implantation using a hardmask A method for processing CMOS wells, and performing multiple ion implantations with the use of a single hard mask is disclosed. The method includes forming and patterning a hardmask over a substrate, whereby the hardmask attains a first opening. The substrate may be ... | 08/23/2011 |
| 7994066 | Si surface cleaning for semiconductor circuits A method is disclosed for the cleaning of a Si surface at low temperatures. Oxide on the Si surface is brought into contact with Ge, which then sublimates off the surface. The Ge contamination remaining after the oxide removal is cleared away by an exposure to an al... | 08/09/2011 |
| 7977965 | Soft error detection for latches A system and method for soft error detection in digital ICs is disclosed. The system includes an observing circuit coupled to a latch, which circuit is capable of a response upon a state change of the latch. The system further includes synchronized clocking provided... | 07/12/2011 |
| 7947549 | Gate effective-workfunction modification for CMOS CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control lay... | 05/24/2011 |
| 7935588 | Enhanced transistor performance by non-conformal stressed layers NFET and PFET devices with separately strained channel regions, and methods of their fabrication is disclosed. A stressing layer overlays the device in a manner that the stressing layer is non-conformal with respect the gate. The non-conformality of the stressing la... | 05/03/2011 |
| 7928875 | Superconductor analog-to-digital converter A superconducting Analog-to-Digital Converter (ADC) employing rapid-single-flux-quantum (RSFQ) logic is disclosed. The ADC has only superconductor active components, and is characterized as being an Nth-order bandpass sigma-delta ADC, with the order “N... | 04/19/2011 |
| 7880243 | Simple low power circuit structure with metal gate and high-k dielectric FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators and metal containing gates. The metal layers of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. Due to the ... | 02/01/2011 |
| 7867866 | SOI FET with source-side body doping An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side do... | 01/11/2011 |
| 7863126 | Fabrication of a CMOS structure with a high-k dielectric layer oxidizing an aluminum layer in PFET region A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blan... | 01/04/2011 |
| 7807525 | Low power circuit structure with metal gate and high-k dielectric FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET dev... | 10/05/2010 |
| 7790566 | Semiconductor surface treatment for epitaxial growth A method is disclosed for preparing a surface of a Group III-Group V compound semiconductor for epitaxial deposition. The III-V semiconductor surface is treated with boron (B) at a temperature of between about 250° C. and about 350° C. A suitable form for supplyin... | 09/07/2010 |
| 7790538 | Integration of strained Ge into advanced CMOS technology A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial deposit... | 09/07/2010 |
| 7741181 | Methods of forming mixed gate CMOS with single poly deposition A method for fabricating metal gate and polysilicon gate FET devices on the same chip is disclosed. The method avoids the use of two separate masks during gate stack fabrication of the differing gates. By using a single mask, tighter NFET to PFET distances can be ac... | 06/22/2010 |
| 7741165 | Polycrystalline SiGe Junctions for advanced devices A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers a... | 06/22/2010 |
| 7733253 | Superconductor multi-level quantizer A superconductor multi-level quantizer is disclosed, which quantizer includes a number N of Josephson junction (JJ) comparators connected in parallel to a common input node. The quantizer further includes at least one flux bias device. Each flux bias device is capab... | 06/08/2010 |
| 7728748 | Superconducting analog-to-digital converter A superconducting bandpass sigma-delta Analog-to-Digital Converter (ADC) is disclosed. The ADC is characterized as being an Nth-order, having N resonators, with N being at least 2. The ADC also may have N−1 amplifiers, where the amplifiers directionally... | 06/01/2010 |
| 7723798 | Low power circuit structure with metal gate and high-k dielectric FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET dev... | 05/25/2010 |
| 7714725 | Method and system for locating a dependent A method and system for locating a dependent by a guardian entity at a locality using RFID technology is disclosed. A RFID tag is situated with the dependent and a plurality of RFID reader devices capable of communicating with the RFID tag are distributed about the ... | 05/11/2010 |
| 7696539 | Device fabrication by anisotropic wet etch A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substan... | 04/13/2010 |
| 7678638 | Metal gated ultra short MOSFET devices MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed o... | 03/16/2010 |
| 7666741 | Corner clipping for field effect devices A method is presented for fabricating a non-planar field effect device. The method includes the production of a Si based material Fin structure that has a top surface substantially in parallel with a {111} crystallographic plane of the Si Fin structure, and the etch... | 02/23/2010 |
| 7659153 | Sectional field effect devices and method of fabrication A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a format... | 02/09/2010 |
| 7655983 | SOI FET with source-side body doping An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side do... | 02/02/2010 |
| 7598897 | Superconductor analog-to-digital converter A superconducting Analog-to-Digital Converter (ADC) employing rapid-single-flux-quantum (RSFQ) logic is disclosed. The ADC has only superconductor active components, and is characterized as being an Nth-order bandpass sigma-delta ADC, with the order “N... | 10/06/2009 |
| 7563657 | High performance FET devices and methods thereof Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a l... | 07/21/2009 |
| 7547930 | High performance FET devices and methods thereof Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a l... | 06/16/2009 |
| 7525161 | Strained MOS devices using source/drain epitaxy NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in t... | 04/28/2009 |
| 7510916 | High performance FET devices and methods thereof Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a l... | 03/31/2009 |
| 7498943 | Method and system for locating a dependent A method and system for locating a dependent by a guardian entity at a locality using RFID technology is disclosed. A RFID tag is situated with the dependent and a plurality of RFID reader devices capable of communicating with the RFID tag are distributed about the ... | 03/03/2009 |
| 7494861 | Method for metal gated ultra short MOSFET devices MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed o... | 02/24/2009 |
| 7413941 | Method of fabricating sectional field effect devices A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a format... | 08/19/2008 |
| 7411214 | High performance FET devices and methods thereof Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a l... | 08/12/2008 |
| 7410844 | Device fabrication by anisotropic wet etch A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substan... | 08/12/2008 |
| 7389530 | Portable electronic door opener device and method for secure door opening A portable computing device for opening a door (an electronic door opener) and a method for its use is disclosed. The computing device has a shared secret key, a standard certificate, means for communicating with the door, and a processor adapted for performing oper... | 06/17/2008 |
| 7388258 | Sectional field effect devices A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a format... | 06/17/2008 |
