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| Number | Title | Issue Date |
| 7790559 | Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes A semiconductor structure and a method for forming the same. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric ... | 09/07/2010 |
| 7714366 | CMOS transistor with a polysilicon gate electrode having varying grain size Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more de... | 05/11/2010 |
| 7635643 | Method for forming C4 connections on integrated circuit chips and the resulting devices A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. I... | 12/22/2009 |
| 7629192 | Passive electrically testable acceleration and voltage measurement devices Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second i... | 12/08/2009 |
| 7615827 | Dual gate dielectric thickness devices and circuits using dual gate dielectric thickness devices Dual thickness devices and circuits using dual gate thickness devices. The devices include: one or more FETs of a first polarity and one or more FETs of a second and opposite polarity, the one or more FETs of the first polarity electrically connected to the one or m... | 11/10/2009 |
| 7607455 | Micro-electro-mechanical valves and pumps and methods of fabricating same Micro-valves and micro-pumps and methods of fabricating micro-valves and micro-pumps. The micro-valves and micro-pumps include electrically conductive diaphragms fabricated from electrically conductive nano-fibers. Fluid flow through the micro-valves and pumping act... | 10/27/2009 |
| 7598166 | Dielectric layers for metal lines in semiconductor chips A semiconductor structure and methods for forming the same. The structure includes (a) a substrate; (b) a first device and a second device each being on the substrate; (c) a device cap dielectric layer on the first and second devices and the substrate, wherein the d... | 10/06/2009 |
| 7585764 | VIA bottom contact and method of manufacturing same A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wir... | 09/08/2009 |
| 7585758 | Interconnect layers without electromigration A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing... | 09/08/2009 |
| 7573085 | Deep trench formation in semiconductor device fabrication A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through t... | 08/11/2009 |
| 7572739 | Tape removal in semiconductor structure fabrication A semiconductor structure fabrication method for removing a tape physically attached to a device side of the semiconductor substrate by an adhesive layer of the tape, wherein the adhesive layer comprises an adhesive material. The method includes the step of submergi... | 08/11/2009 |
| 7572650 | Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electri... | 08/11/2009 |
| 7563714 | Low resistance and inductance backside through vias and methods of fabricating same A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; f... | 07/21/2009 |
| 7562237 | Semiconductor integrated circuit device with internal power control system One object of the present invention is to provide an LSI that can dynamically perform appropriate adjustment for a power voltage to be supplied to an internal circuit, not only at the time of the occurrence of the initial change of a performance due to a variation o... | 07/14/2009 |
| 7560753 | Field effect transistor with thin gate electrode and method of fabricating same A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of... | 07/14/2009 |
| 7557023 | Implantation of gate regions in semiconductor device fabrication A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate di... | 07/07/2009 |
| 7547576 | Solder wall structure in flip-chip technologies A structure and method for forming the same. The semiconductor structure includes a first semiconductor chip and N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer. The semiconductor structure also includes a... | 06/16/2009 |
| 7541613 | Methods for reducing within chip device parameter variations A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measu... | 06/02/2009 |
| 7541247 | Guard ring structures for high voltage CMOS/low voltage CMOS technology using LDMOS (lateral double-diffused metal oxide semiconductor) device fabrication A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate. The method further includes simultaneously forming a first doped transistor region o... | 06/02/2009 |
| 7539968 | Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints An approach that iteratively synthesizes an integrated circuit design to attain power closure is described. In one embodiment, the integrated circuit design is initially synthesized to satisfy timing and power constraints. Results from the initial synthesis are fed ... | 05/26/2009 |
| 7531059 | Cleaning of semiconductor wafers by contaminate encapsulation An apparatus and method are provided for removing contaminate particulate matter from substrate surfaces such as semiconductor wafers. The method and apparatus use a material, preferably a liquid curable polymer, which is applied as a sacrificial coating to the surf... | 05/12/2009 |
| 7521735 | Multiple layer and crystal plane orientation semiconductor substrate A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline... | 04/21/2009 |
| 7517789 | Solder bumps in flip-chip technologies A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conductive bond pad on and in direct physical contact with the dielectric layer top surface; (c) a pat... | 04/14/2009 |
| 7516426 | Methods of improving operational parameters of pair of matched transistors and set of transistors Methods of improving operational parameters between at least a pair of matched transistors, and a set of transistors, are disclosed. One embodiment of a method includes a method of improving at least one of a threshold voltage (Vt) mismatch and current drive between... | 04/07/2009 |
| 7511378 | Enhancement of performance of a conductive wire in a multilayered substrate An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically ... | 03/31/2009 |
| 7505110 | Micro-electro-mechanical valves and pumps Methods of fabricating micro-valves and micro-pumps. The micro-valves and micro-pumps that are fabricated include electrically conductive diaphragms fabricated from electrically conductive nano-fibers. Fluid flow through the micro-valves and pumping action of the mi... | 03/17/2009 |
| 7501690 | Semiconductor ground shield method A ground shield is disclosed that includes a ‘cheesed’ metal positioned within a dielectric layer and a metal region positioned within a first metal level over the cheesed metal. The ground shield can have different forms depending on the metal used, and provisi... | 03/10/2009 |
| 7492029 | Asymmetric field effect transistors (FETs) A semiconductor structure. The structure includes (a) a semiconductor channel region, (b) a semiconductor source block in direct physical contact with the semiconductor channel region; (c) a source contact region in direct physical contact with the semiconductor sou... | 02/17/2009 |
| 7492046 | Electric fuses using CNTs (carbon nanotubes) A fuse structure and a method for operating the same. The fuse structure operating method includes providing a structure. The structure includes (a) an electrically conductive layer and (b) N electrically conductive regions hanging over without touching the electric... | 02/17/2009 |
| 7491631 | Method of doping a gate electrode of a field effect transistor A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface; forming an island on the top surface of... | 02/17/2009 |
| 7491589 | Back gate FinFET SRAM A compact semiconductor structure having back gate(s) for controlling threshold voltages and associated method of formation is disclosed. Fabrication of the semiconductor structure starts with a semiconductor region formed directly on an underlying electrically isol... | 02/17/2009 |
| 7485965 | Through via in ultra high resistivity wafer and related methods A through via in an ultra high resistivity wafer and related methods are disclosed. A method for forming a through via comprises: providing a semiconductor wafer including a first silicon layer, a buried dielectric layer, and a substrate; forming a device on the fir... | 02/03/2009 |
| 7482675 | Probing pads in kerf area for wafer testing A structure and a method for forming the same. The structure includes (a) a substrate having a top substrate surface; (b) an integrated circuit on the top substrate surface, wherein the integrated circuit includes a bond pad electrically connected to a transistor of... | 01/27/2009 |
| 7483285 | Memory devices using carbon nanotube (CNT) technologies Structures for memory devices. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential... | 01/27/2009 |
| 7474104 | Wafer-to-wafer alignments Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The firs... | 01/06/2009 |
| 7473593 | Semiconductor transistors with expanded top portions of gates A method for forming a semiconductor transistor with an expanded top portion of a gate The gate is expanded through implanting atoms in the top portion of transistor's gate electrode region. The transistor formed includes a semiconductor region having two source/dra... | 01/06/2009 |
| 7470613 | Dual damascene multi-level metallization A method for forming an interconnect structure, the interconnect structure comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the... | 12/30/2008 |
| 7462509 | Dual-sided chip attached modules An method of packaging an electronic device. The method for packaging the device including: providing a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and... | 12/09/2008 |
| 7462528 | CMOS (Complementary metal oxide semiconductor) technology with leakage current mitigation A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the... | 12/09/2008 |
| 7459785 | Electrical interconnection structure formation An electrical interconnection structure. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metalli... | 12/02/2008 |
