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Attorney: Rutkowski; Peter T., Donaldson; Richard L., Hiller; William E.


Number of patents: 17
Last date: March 03, 1998

NumberTitleIssue Date
5723988CMOS with parasitic bipolar transistor
A device is disclosed which combines the advantages of CMOS and bipolar using an existing parasitic bipolar device. As such high on-chip density is attainable with the device along with high speed capability while maintaining low power advantages....
03/03/1998
5508637Logic module for a field programmable gate array
An 8-input, 1-output mux-based logic module for an FPGA is disclosed. The logic module comprises five separate multiplexers connected differently in the various embodiments of the present invention. The 8-input logic module can realize a total of 2390 uni...
04/16/1996
5502402FPGA architecture based on a single configurable logic module
A logic module uses a multiplexer which can be used to configure the logic module as combinational or sequential. A sequential block comprises a flip-flop with preset and clear, and can be SR or D-type. The multiplexer is used in the feedback loop of the ...
03/26/1996
5458732Method and system for identifying process conditions
A plasma processing system 10 for fabricating a semiconductor wafer 24 is disclosed. The system includes a plasma processing tool 12 and an RF energy source 20 coupled to the plasma processing tool 12. An optional matching network 22 may be included betwe...
10/17/1995
5451909Feedback amplifier for regulated cascode gain enhancement
A regulated cascode circuit with enhanced gain includes a cascode section including a common source MOS transistor (m1) of a first polarity and a cascode device (m2) wherein the drain of the common-source MOS transistor (m1
09/19/1995
5441902Method for making channel stop structure for CMOS devices
In a semiconductor device having two N type regions separated by a P type region, a channel stop is needed to prevent shorting between the two N type regions. The channel stop of the invention has oxide isolators over the two N type regions and a P+ type ...
08/15/1995
5435379Method and apparatus for low-temperature semiconductor processing
A chilling system (12) has a container (20) filled with a coolant (22). A pipe (16) traverses within the container (20) and the coolant (22) to a housing (18). Fluid flows within the pipe (16) and becomes chilled through the pipe (16) upon entering the co...
07/25/1995
5429955Method for constructing semiconductor-on-insulator
A method for constructing a semiconductor-on-insulator is provided. A sacrificial layer (12) of a predetermined thickness is first formed on a semiconductor wafer (10) surface. The wafer (10) is then subjected to an ion implantation process to place the i...
07/04/1995
5422723Diffraction gratings for submicron linewidth measurement
A test structure and a method of using it for measuring submicron linewidths. Diffraction gratings are made with lines having an unknown linewidth. The grating has a pitch comprises of multiple lines and multiple spaces. This permits a wider "effective pi...
06/06/1995
5414310Analog voltage maximizer and minimizer circuits
Voltage minimizer and maximizer circuits are provided for both single-ended and fully-differential analog input voltages. A single-ended analog voltage maximizer circuit includes a plurality of operational amplifiers (OP1, OP2 . . . ...
05/09/1995
5404327Memory device with end of cycle precharge utilizing write signal and data transition detectors
A memory device (10) having a precharge and timing control circuit (24) is configured so that a precharge state occurs at the end of memory cycles. A precharge signal remains active until a change of address is detected by an address transition detector (...
04/04/1995
5397962Source and method for generating high-density plasma with inductive power coupling
A source and method for generating high density plasma with inductive radio-frequency power coupling is provided in which coil antenna sections (34) within a plasma source (12) are used to generate a high-density uniform plasma. This plasma is then guided...
03/14/1995
5397909High-performance insulated-gate field-effect transistor
An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate elec...
03/14/1995
5338969Unerasable programmable read-only memory
An unerasable memory cell (10) is formed in the face of a layer (22) of semiconductor of a first conductivity type and includes an erasable read-only memory cell (12) having a first source/drain region (16) and a second source/drain region (18) of a secon...
08/16/1994
5294801Extended source e-beam mask imaging system including a light source and a photoemissive source
An electron beam imaging system (10) includes a photoemitter plate (12). An optical image beam (15) is directed through a pattern mask (18), which is imaged onto the photoemitter (12). The photoemitter (12) emits electrons from those unmasked regions illu...
03/15/1994
5287304Memory cell circuit and array
An improved memory cell (118) is provided which may be incorporated into an array (202) of memory cells. Array (202) includes a first gate conductor region (224) and a second gate conductor region (238), wherein the first and second gate conductor regions...
02/15/1994
5274588Split-gate cell for an EEPROM
A non-volatile memory cell includes heavily doped source 12 and drain 14 regions separated by a channel region 16. The source 12 and drain 14 are isolated from floating gate 18 and control gate 22 by thick oxide 36. A floating gate 18 is formed over and i...
12/28/1993
 
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