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| Number | Title | Issue Date |
| 7069228 | Apparatus and method for an internet based computer reservation booking system The present invention is a software product that provides merchants that sell time-slot inventories tools to capitalize on the Internet revolution. The present invention enables the creation of web-sites for merchants with a built-in web-based reservation booking sy... | 06/27/2006 |
| 5956747 | Processor having a plurality of pipelines and a mechanism for maintaining coherency among register values in the pipelines A processor is disclosed. The processor includes a processing unit with a plurality of pipelines. Each of the pipelines execute instructions which may define source register values and destination register values from a register file. A plurality of memor... | 09/21/1999 |
| 5875339 | Asynchronous arbiter using multiple arbiter elements to enhance speed An arbiter circuit having a plurality of mutual exclusion (MUTEX) elements is disclosed. Each of the MUTEX elements is coupled to receive a different combination of request signals and their complements and grant signals and their complements fed back fro... | 02/23/1999 |
| 5713025 | Asynchronous arbiter using multiple arbiter elements to enhance speed An arbiter circuit is described that is capable of granting a first user access to a shared resource while concurrently arbitrating subsequent requests from the first user to other users seeking access to the shared resource. The arbiter of the present in... | 01/27/1998 |
| 5682493 | Scoreboard table for a counterflow pipeline processor with instruction packages and result packages A counterflow pipeline having a scoreboard table and a register file is disclosed. In the counterflow pipeline, information flows in two directions. Instructions flow up the pipeline during execution. The results from previous instructions flow down the s... | 10/28/1997 |
| 5675529 | Fast access memory array A memory array with improved access time is disclosed. In one embodiment, the memory array includes a plurality of memory cells arranged in rows and columns. Each one of the plurality of columns includes a global bit line, a local bit line with a memory c... | 10/07/1997 |
| 5510732 | Synchronizer circuit and method for reducing the occurrence of metastability conditions in digital systems A digital system including a synchronizer circuit which significantly reduces the occurrence of metastability conditions during data transfer between a first digital subsystem and a second digital subsystem is disclosed. The synchronizer circuit includes ... | 04/23/1996 |
| 5430399 | Reset logic circuit and method A high speed inverter circuit is disclosed. The inverter has a quiescent state, a set state for receiving an input pulse and generating a set pulse in response thereto, a reset stage in which a delayed version of the same input pulse is used to reset the ... | 07/04/1995 |
| 5402386 | Word line decoder/driver circuit and method A row select circuit for semiconductor memories is disclosed. The row select circuit includes a decoder portion and a driver portion. The decoder potion of the row select circuit includes a plurality of decoder circuits, each servicing a multiplicity of r... | 03/28/1995 |
| 5381377 | Word line driver circuit and method A driver circuit for use in a semiconductor memory array is disclosed. The memory array includes a plurality of the driver circuits, each used to drive a word line in the memory array. The driver circuit of the present invention includes a pull up portion... | 01/10/1995 |
| 5380956 | Multi-chip cooling module and method A liquid cooling module for semiconductor chips is disclosed. The module includes a plurality of substrates, each containing at least one chip. The substrates are arranged in the module so that when coolant flows through the module, the coolant is exposed... | 01/10/1995 |
| 5355032 | TTL to CMOS translator circuit and method A high speed, low powered, BiCMOS TTL to CMOS translator circuit and method which relies on an internally generated reference voltage and which is capable of driving high loads. The translator circuit includes a first inverting and translating stage havin... | 10/11/1994 |
| 5068551 | Apparatus and method for translating ECL signals to CMOS signals The present invention provides an ECL to CMOS level translation circuit which uses a dynamic, internally generated reference voltage to translate ECL level signals into CMOS level signals. The translator includes an input translation circuit which uses em... | 11/26/1991 |
| 5060389 | Semiconductor device inspection template A semiconductor device inspection template for use in visual inspection of semiconductor die or packages includes a selectively patterned transparent film mounted in a sleeve adapted for rapid placement and removal from an optical inspection instrument's ... | 10/29/1991 |
