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| Number | Title | Issue Date |
| 7461205 | Performing useful computations while waiting for a line in a system with a software implemented cache Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes original source code, and while compiling the source code, inserts explicit... | 12/02/2008 |
| 7457974 | Dynamically changing PCI clocks A method, apparatus and computer-usable medium are presented for dynamically selecting a clock signal used by a peripheral device that is coupled to a motherboard. When the motherboard is powered off, a clock selector sends the peripheral device an internal clock si... | 11/25/2008 |
| 7447725 | Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second ... | 11/04/2008 |
| 7447602 | System and method for sorting processors based on thermal design point A system and method for sorting processor chips based on a thermal design point are provided. With the system and method, for each processor chip, a high power workload is run on the processor chip to determine a voltage regulator module (VRM) load line. Thereafter,... | 11/04/2008 |
| 7444632 | Balancing computational load across a plurality of processors Source code subtasks are compiled into byte code subtasks whereby the byte code subtasks are translated into processor-specific object code subtasks at runtime. The processor-type selection is based upon one of three approaches which are 1) a brute force approach, 2... | 10/28/2008 |
| 7444435 | Non-fenced list DMA command mechanism A DMA controller (DMAC) for handling a list DMA command in a computer system is provided. The computer system has at least one processor and a system memory, the list DMA command relates to an effective address (EA) of the system memory, and the at least one process... | 10/28/2008 |
| 7434182 | Method for testing sub-systems of a system-on-a-chip using a configurable external system-on-a-chip A method is provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expe... | 10/07/2008 |
| 7434127 | eFuse programming data alignment verification apparatus and method An eFuse data alignment verification apparatus and method are provided. Alignment latches are provided in a series of latch units of a write scan chain and a logic unit is coupled to the alignment latches. A sequence of data that is scanned-into the series of latch ... | 10/07/2008 |
| 7434033 | Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed... | 10/07/2008 |
| 7430580 | Method and apparatus for adding recipients to sent email A data processing system for resending a previously sent email message. A new recipient for the previously sent email message is selected. The new recipient of the previously sent email message is added in response to selecting the new recipient, wherein the previou... | 09/30/2008 |
| 7430487 | System and method for implementing a programmable DMA master with data checking utilizing a drone system controller A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a ... | 09/30/2008 |
| 7430264 | Method to reduce transient current swings during mode transitions of high frequency/high power chips A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances a... | 09/30/2008 |
| 7421453 | Asynchronous linked data structure traversal Asynchronously traversing a disjoint linked data structure is presented. A synergistic processing unit (SPU) includes a handler that works in conjunction with a memory flow controller (MFC) to traverse a disjoint linked data structure. The handler compares a search ... | 09/02/2008 |
| 7420378 | Power grid structure to optimize performance of a multiple core processor A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and... | 09/02/2008 |
| 7417480 | Duty cycle correction circuit whose operation is largely independent of operating voltage and process A Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed... | 08/26/2008 |
| 7414436 | Limited switch dynamic logic cell based register A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the fron... | 08/19/2008 |
| 7409469 | Multi-chip digital system having a plurality of controllers with input and output pins wherein self-identification signal are received and transmitted The present invention provides for a system, comprising a controller and a processor. The controller comprises at least an output pin and a plurality of input pins, and is configured to receive self-identify control signals through one or more of the plurality of in... | 08/05/2008 |
| 7406640 | Method and apparatus for testing a ring of non-scan latches with logic built-in self-test A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic... | 07/29/2008 |
| 7406589 | Processor having efficient function estimate instructions High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instr... | 07/29/2008 |
| 7401242 | Dynamic power management in a processor design A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle d... | 07/15/2008 |
| 7395531 | Framework for efficient code generation using loop peeling for SIMD loop code with multiple misaligned statements A system and method is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In this framework, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler... | 07/01/2008 |
| 7395174 | Generation of software thermal profiles executed on a set of processors using thermal sampling A computer implemented method, data processing system, and computer usable code are provided for generation of software thermal profiles for applications executing on a set of processors using thermal sampling. Sampling is performed of the thermal states of the set ... | 07/01/2008 |
| 7392511 | Dynamically partitioning processing across plurality of heterogeneous processors A program is into at least two object files: one object file for each of the supported processor environments. During compilation, code characteristics, such as data locality, computational intensity, and data parallelism, are analyzed and recorded in the object fil... | 06/24/2008 |
| 7392441 | Method of performing operational validation with limited CPU use of a communications network A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a plurality of devices exchanging data during a test. When the test is re... | 06/24/2008 |
| 7392419 | System and method automatically selecting intermediate power supply voltages for intermediate level shifters The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal... | 06/24/2008 |
| 7392270 | Apparatus and method for reducing the latency of sum-addressed shifters The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a b... | 06/24/2008 |
| 7389508 | System and method for grouping processors and assigning shared memory space to a group in heterogeneous computer environment A system and method for grouping processors is presented. A processing unit (PU) initiates an application and identifies the application's requirements. The PU assigns one or more synergistic processing units (SPUs) and a memory space to the application in the form ... | 06/17/2008 |
| 7389419 | Methods for supplying cryptographic algorithm constants to a storage-constrained target The present invention provides for authenticating a message. A security function is performed upon the message. The message is sent to a target. The output of the security function is sent to the target. At least one publicly known constant is sent to the target. Th... | 06/17/2008 |
| 7389363 | System and method for flexible multiple protocols A system and method for flexible multiple protocols are presented. A device's logical layer may be dynamically configured on a per interface basis to communicate with external devices in a coherent or a non-coherent mode. In coherent mode, commands such as coherency... | 06/17/2008 |
| 7386887 | System and method for denying unauthorized access to a private data processing network Systems and methods for denying access to a data processing system by an intruder are provided. Input/output (I/O) on the intruder's connection may be taken over and responses mimicking a local terminal session passed back. On an attempted reconnect by the intruder,... | 06/10/2008 |
| 7386636 | System and method for communicating command parameters between a processor and a memory flow controller A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controlle... | 06/10/2008 |
| 7386414 | Generation of hardware thermal profiles for a set of processors A computer implemented method, data processing system, and computer usable code are provided for generation of hardware thermal profiles for a set of processors. Sampling is performed of the thermal states of the set of processors during the execution of a set of wo... | 06/10/2008 |
| 7386759 | Method of performing functional validation testing A system, apparatus, computer program product and method of performing functional validation testing in a system are provided. Generally, functional validation testing includes data acquisition and data validation testing. During the functional validation testing tw... | 06/10/2008 |
| 7380083 | Memory controller capable of locating an open command cycle to issue a precharge packet A memory controller capable of locating an open command cycle for the purpose of issuing a precharge packet to extreme data rate (XDR) dynamic random access memory (DRAM) devices is disclosed. In response to a receipt of two request packets concurrently, a determina... | 05/27/2008 |
| 7380052 | Reuse of functional data buffers for pattern buffers in XDR DRAM A method, an apparatus, and a computer program are provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buf... | 05/27/2008 |
| 7376532 | Maximal temperature logging A computer implemented method, data processing system, and processor are provided for logging a maximal temperature in an integrated circuit. A digital thermal sensor senses a temperature in the integrated circuit. The sensed temperature of the digital thermal senso... | 05/20/2008 |
| 7376816 | Method and systems for executing load instructions that achieve sequential load consistency A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, ... | 05/20/2008 |
| 7376875 | Method of improving logical built-in self test (LBIST) AC fault isolations A system, apparatus and method of isolating a plurality of limiting logical cones in a chip during a logical built-in self test (LBIST) are provided. An LBIST is performed on the chip in order to locate a first latch that fails the test. Particularly, latches on the... | 05/20/2008 |
| 7373573 | Apparatus and method for using a single bank of eFuses to successively store testing data from multiple stages of testing An apparatus and method for using a single bank of electric fuses (eFuses) to successively store test data derived from multiple stages of testing are provided. To encode and store array redundancy data from each subsequent test in the same bank of eFuses, a latch o... | 05/13/2008 |
| 7370176 | System and method for high frequency stall design A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructi... | 05/06/2008 |
