Bizarre Patents
User-operated amusement apparatus for kicking the user's buttocks
An apparatus including a user-operated and controlled apparatus for self-infliction of repetitive blows to the user's buttocks by a plurality of elongated arms bearing flexible extensions that rotate under the user's control.
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| Number | Title | Issue Date |
| 4337497 | Device for detecting the direction and change of rotational speed of a rotating element Device for detecting the direction and change of rotational speed of a rotating element. In one embodiment, a pair of phototransistors which are energized by a light source according to an ordered sequence through a disk formed by opaque and transparent s... | 06/29/1982 |
| 4321668 | Prediction of number of data words transferred and the cycle at which data is available A microprogrammed data processing system includes a cache memory, a decimal unit and an execution unit. The decimal unit receives operands from cache memory, strips the non-decimal digit information from the operands, and assembles the 4-bit decimal digit... | 03/23/1982 |
| 4321665 | Data processing system having centralized data alignment for I/O controllers In a data processing system which includes a central processing unit (CPU), main memory and a plurality of input/output controllers (IOCs) connected to a common bus information can be transferred between the main memory and CPU and main memory and the IOC... | 03/23/1982 |
| 4305134 | Automatic operand length control of the result of a scientific arithmetic operation Mantissa results of floating point operations are truncated to words of 24 bits each by storing the 64 bit mantissa result in a first address location of a random access memory, and storing binary ZEROs in the 48 least significant bit positions of a secon... | 12/08/1981 |
| 4303993 | Memory present apparatus A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned in a number of physical row locations together providing a predetermined... | 12/01/1981 |
| 4300194 | Data processing system having multiple common buses Multiple common buses are provided for coupling a plurality of units in a data processing system for the transfer of information therebetween. The central processing unit (CPU) allocates the multiple common buses to one of the units in response to bus req... | 11/10/1981 |
| 4298956 | Digital read recovery with variable frequency compensation using read only memories Digital data is recorded on the surface of a magnetic media such as a disk or diskette in the form of magnetic flux transitions identifying clock and data information in a modified frequency modulation (MFM) mode. A read head senses the flux transitions w... | 11/03/1981 |
| 4298935 | Interface circuit for coupling an automated maintenance system to a CPU Apparatus for use in coupling an automated maintenance system of general utility to a central processing unit of a data processing system. The interface apparatus is comprised of path control and operational condition control registers to control and enab... | 11/03/1981 |
| 4296465 | Data mover A data mover for moving blocks of data stored in a first location of the working store of a data processing system to a second location in the working store. The data mover is provided with the necessary registers, switches, counters and control circuits ... | 10/20/1981 |
| 4295203 | Automatic rounding of floating point operands If the firmware calls for an operand rounding operation, apparatus in the Scientific Instruction Processor (SIP) tests the bit to the right of the low order bit of the normalized operand to determine if a rounding cycle is required. If the operand require... | 10/13/1981 |
| 4295202 | Hexadecimal digit shifter output control by a programmable read only memory A Scientific Instruction Processor (SIP) uses a Programmable Read Only Memory (PROM) to control the output of a two stage shifter. The shifter performs the necessary mantissa shift operations of shift right, shift left, shift right around, as well as inse... | 10/13/1981 |
| 4293908 | Data processing system having direct memory access bus cycle In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchro... | 10/06/1981 |
| 4292668 | Data processing system having data multiplex control bus cycle In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchro... | 09/29/1981 |
| 4285035 | Apparatus and method for rewrite data insertion in a three descriptor instruction In a microprogrammed data processing system in which the boundaries of the operands or data strings identified by the descriptors are not constrained to coincide with boundaries of the units of addressable memory space, i.e., words, the time required to r... | 08/18/1981 |
| 4277831 | Computer aided wire wrap operator check system There is disclosed herein an apparatus for computerized real time verification of the correctness of pin locations for wire wrap connections made by human operators in constructing or upgrading computer backplanes. A suitably programmed microprocessor ope... | 07/07/1981 |
| 4276596 | Short operand alignment and merge operation In a microprogrammed data processing system, the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which, in response to a microword indicating that the result of the decimal numeric calculation is a ... | 06/30/1981 |
| 4273859 | Method of forming solder bump terminals on semiconductor elements An improved method of forming raised input/output (I/O) terminals on the top surfaces of semiconductor elements of a semiconductor wafer. After via openings are formed through the passivation layer of such elements at locations where the I/O terminals are... | 06/16/1981 |
| 4271467 | I/O Priority resolver Apparatus for resolving the priority of a plurality of input/output devices. The device request signals and signals indicating the channel number of the currently active channel program are applied to the address terminals of a programmable read only memo... | 06/02/1981 |
| 4271472 | Wire wrap operator check system There is disclosed herein an apparatus for verifying the correct placement of a wire wrap tool on a wire wrap pin in an array of pins. An outside source of pin and condition data such as a human operator operating switches or a mechanical sequential state... | 06/02/1981 |
| 4268909 | Numeric data fetch - alignment of data including scale factor difference In a microprogrammed data processing system, the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which is conditioned by the instruction descriptors in advance of receiving the operands to align the... | 05/19/1981 |
| 4268907 | Cache unit bypass apparatus A cache unit includes a cache store organized into a number of levels to provide a fast access to instructions and data words. Directory circuits, associated with the cache store, contain address information identifying those instructions and data words s... | 05/19/1981 |
| 4266285 | Row selection circuits for memory circuits A memory subsystem includes a memory board comprising of a number of memory chips positioned at a corresponding number of physical row locations. The memory chips are one of two types selected to provide a predetermined memory capacity. The board further ... | 05/05/1981 |
| 4263648 | Split system bus cycle for direct memory access of peripherals in a cathode ray tube display system Apparatus in a Cathode Ray Tube (CRT) display allows the sharing of the system bus between the microprocessor (CPU) and Direct Memory Access (DMA) devices without degrading the CPU performance by splitting the system bus cycle into an address phase and a ... | 04/21/1981 |
| 4261035 | Broadband high level data link communication line adapter A hardware/firmware communication line adapter for interfacing a communication processor to a broadband high level data link communication channel. Transmit and receive data and control characters received either from the processor or from a communication... | 04/07/1981 |
| 4255852 | Method of constructing a number of different memory systems A printed circuit board assembly includes at least two layers which is able to accommodate a subsystem such as a memory subsystem designed to have one or more optional features. The two layers of the printed circuit board when etched include the required ... | 03/17/1981 |
| 4257101 | Hardware in a computer system for maintenance by a remote computer system A remote maintenance apparatus for performing maintenance via a communication channel. Hardware is provided to retain information in a special channel which can be accessed by a remote communication system, in the event of malfunction in the computer syst... | 03/17/1981 |
| 4255786 | Multi-way vectored interrupt capability A multi-way vectored interrupt automatically addresses any one of a plurality of locations in a memory according to a unique function code. Hardware is provided which disables the normal paging addressing apparatus of a processor and enables an indirect a... | 03/10/1981 |
| 4254462 | Hardware/firmware communication line adapter A hardware/firmware control system is disclosed for accommodating the concurrent bi-directional transfer of information between a communications channel such as a telephone line and a communications processor in a data processing system.... | 03/03/1981 |
| 4250548 | Computer apparatus Computer apparatus in a word organized computer system for implementing a single computer instruction for moving a binary number stored in one of a plurality of addressable registers to a designated memory location in a word addressable memory. The binary... | 02/10/1981 |
| 4249172 | Row address linking control system for video display terminal A logic control system for a video display terminal is disclosed for accommodating vertically and horizontally varying entry points to a video memory to acquire first character bytes of rows of video information for display on a CRT screen. Dynamically ch... | 02/03/1981 |
| 4247941 | Simulator for bit and byte synchronized data network A data communication simulator system wherein the basic operational conditions of a bit and byte synchronized data network may be simulated by generation of a bit timing signal, a byte timing signal, data signals, and control and status indication signals... | 01/27/1981 |
| 4247891 | Leading zero count formation In a microprogrammed data processing system, the throughput of the system is increased by apparatus which counts the number of leading zero digits of an operand on the cycle in which the operand word is processed through the decimal unit and sends that co... | 01/27/1981 |
| 4246644 | Vector branch indicators to control firmware In a microprogrammed data processing system the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which indicates to the microprogram the characteristics of the operand being processed. This enables t... | 01/20/1981 |
| 4245263 | Write precompensation and write encoding for FM and MFM recording Information to be written in the form of magnetic flux reversals on the surface of a disk or diskette is applied in serial fashion to a first shift registor. The parallel outputs of the shift register address a PROM. The PROM output is applied to a second... | 01/13/1981 |
| 4245304 | Cache arrangement utilizing a split cycle mode of operation A cache system includes a high speed storage unit organized into a plurality of levels, each including a number of multiword blocks and at least one multiposition address selection switch and address register. The address switch is connected to receive ad... | 01/13/1981 |
| 4245328 | Binary coded decimal correction apparatus for use in an arithmetic unit of a data processing unit Binary coded decimal operands may be operated on by use of a binary arithmetic logic unit and the result corrected to provide a binary coded decimal result by use of correction logic which is responsive to the result produced by the binary arithmetic logi... | 01/13/1981 |
| 4245299 | System providing adaptive response in information requesting unit In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority unit during an asynchronously generated bus trans... | 01/13/1981 |
| 4241446 | Apparatus for performing single error correction and double error detection This relates to an apparatus for performing single error correction, double error detection of binary words, each section of the apparatus processing one byte of raw data. Each section includes first logic means for producing a first plurality of intermed... | 12/23/1980 |
| 4241418 | Clock system having a dynamically selectable clock period A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a delay line coupled to an INVERTER. By using a ... | 12/23/1980 |
| 4240144 | Long operand alignment and merge operation In a microprogrammed data processing system, the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which receives a long operand, greater than a predetermined number of words, which is the result of t... | 12/16/1980 |
