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| Number | Title | Issue Date |
| 4749989 | Word processing composite character processing method A method for printing composite characters in a word processing system by multistriking two or more characters in the same character space. This method allows composite character graphics to be produced by using individual character graphics found within ... | 06/07/1988 |
| 4750114 | Local area network control block Local area network control block (LCB) hardware and a method is disclosed which forms a prime vehicle of intercommunication between controller coupled local area networks (LANs), comprising a plurality of computer systems. An LCB has a predetermined forma... | 06/07/1988 |
| 4694394 | Microprocessor system having a multiplexed address/data bus which communicates with a plurality of memory and input/output devices including TTL output gates A microprocessor system is disclosed wherein a microprocessor has a multiplexed address/data bus which communicates with a plurality of memory and input/output devices. A demultiplexing register permits the demultiplexing of the microprocessor address/dat... | 09/15/1987 |
| 4559595 | Distributed priority network logic for allowing a low priority unit to reside in a high priority position In a data processing system, a bus is provided for the transfer of information between units coupled to the bus. The units are coupled in a priority arrangement which is distributed thereby providing priority logic in each of the units and allowing bus tr... | 12/17/1985 |
| 4558409 | Digital apparatus for synchronizing a stream of data bits to an internal clock An apparatus for decoding and synchronizing data wherein only logic ZERO data bits are received as electronic pulses, each pulse alternating in opposite directions and wherein logic ONE data bits are received as no pulse. The synchronization logic include... | 12/10/1985 |
| 4556840 | Method for testing electronic assemblies A method for achieving printed circuit (PC) board-level testability through electronic component-level design using available technological methods to effect a state of transparency during test, allowing precise verification and diagnosis on a component-b... | 12/03/1985 |
| 4554598 | Single revolution disk sector formatter A track of a disk device is formatted on a single revolution of the disk by using a read only memory (ROM) to store control codes and a random access memory (RAM) to store address field and data field bytes. A DMA controller simultaneously addresses ROM a... | 11/19/1985 |
| 4554445 | Digital pulse stretcher An apparatus for varying the pulse width of a computer clock by adding a predetermined amount of time to the clock pulse width. A synchronous counter is combined with a latch into a circuit whereby a pulse input to the circuit resets both the latch and co... | 11/19/1985 |
| 4545010 | Memory identification apparatus and method A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section ... | 10/01/1985 |
| 4543629 | Apparatus for maximizing bus utilization An interactive terminal computer system is disclosed having a system bus for communicating between elements of the computer system which has apparatus for permitting the execution of a maximum number of concurrent bus cycles without interference with each... | 09/24/1985 |
| 4542517 | Digital serial interface with encode logic for transmission An apparatus for encoding data for serial transmission wherein only logic ZEROs are transmitted as electronic pulses, each pulse alternating in opposite direction and wherein logic ONEs require no pulse.... | 09/17/1985 |
| 4535330 | Bus arbitration logic An interactive computer terminal system having a bus for communication between elements of the system is disclosed having apparatus for assigning control of the computer bus on a predetermined order of priority. The CPU receives requests from computer sys... | 08/13/1985 |
| 4535404 | Method and apparatus for addressing a peripheral interface by mapping into memory address space A method and apparatus for addressing a peripheral interface by mapping into the memory address space of a processor contained in a peripheral controller. The processor in the peripheral controller initializes interface logic within the peripheral control... | 08/13/1985 |
| 4534044 | Diskette read data recovery system A diskette read data recovery system generates a clock which is locked to an incoming data stream. In a phase locked loop, a signal generated by an oscillator and frequency dividers is compared in phase to the incoming data stream to provide first or seco... | 08/06/1985 |
| 4527251 | Remap method and apparatus for a memory system which uses partially good memory devices A remapping method and apparatus is employed by a memory controller system which includes a microprocessing section which couples to a memory section. The memory section includes a partially good bulk random access memory constructed from a plurality of b... | 07/02/1985 |
| 4524416 | Stack mechanism with the ability to dynamically alter the size of a stack in a data processing system In a data processing system, a stack mechanism creates a stack of operands in a series of memory locations. The memory locations are grouped into stack frames corresponding to the operands included within individual procedures executed by a processing uni... | 06/18/1985 |
| 4523313 | Partial defective chip memory support system A memory controller includes a partial defective bulk random access memory having a number of word locations constructed from a plurality of bit wide chips containing a predefined small number of random row or column faults. System columns of chips are or... | 06/11/1985 |
| 4521848 | Intersystem fault detection and bus cycle completion logic system An error detection system is disclosed for not only indicating but eliminating certain errors which may occur during the transfer of information between communication busses in a data processing system wherein plural communication busses each provide a co... | 06/04/1985 |
| 4521849 | Programmable hit matrices used in a hardware monitoring interface unit A hardware monitoring interface unit (HMIU) is coupled to a data processing unit and receives all information transferred between subsystems of the data processing unit. Programmable hit matrices (PHM's) include input latches for receiving the information... | 06/04/1985 |
| 4520356 | Display video generation system for modifying the display of character information as a function of video attributes A video generation logic for a display controller includes a precoded PROM which combines visual attributes associated with the characters of information to be displayed on the display screen to produce multiple video control signals for modifying the dot... | 05/28/1985 |
| 4514806 | High speed link controller wraparound test logic An interactive terminal system includes a high speed link controller (HSLC) and a number of work stations, all coupled in common to a single conductor coaxial bus. The HSLC includes apparatus controlled by a microprocessor to put the HSLC in a wraparound ... | 04/30/1985 |
| 4514820 | Apparatus for generating trapezoidal signals over a single conductor coaxial bus A high speed link controller (HSLC) and a number of work stations are coupled in common to a single conductor coaxial cable. Apparatus generates data signals at high speed for transfer of information between the link controller and the work stations with ... | 04/30/1985 |
| 4513392 | Method and apparatus for generating a repetitive serial pattern using a recirculating shift register A method and apparatus for generating a repetitive serial pattern using a recirculating shift register. Use of a recirculating shift register during a disk formatting operation permits a reduction in the amount of memory contained in a peripheral controll... | 04/23/1985 |
| 4511960 | Data processing system auto address development logic for multiword fetch An auto address development logic that, when provided a starting address, is used to develop consecutive addresses as multiple words of information are presented, one word at a time, during multiple consecutive information transfer cycles. The logic retai... | 04/16/1985 |
| 4509121 | Apparatus for synchronizing a stream of data bits received over a single coaxial conductor A data processing system includes a high speed link controller coupled to a number of work stations by a single coaxial conductor. Apparatus including a counter, a comparator and an adder in the high speed controller synchronizes the data bits received fr... | 04/02/1985 |
| 4509118 | Method and apparatus for defining magnetic disk track field lengths using a programmable counter A method and apparatus for defining magnetic disk track field lengths using a programmable counter. Use of a programmable counter in a disk controller permits a reduction in the amount of combinational logic that would otherwise be required to be able to ... | 04/02/1985 |
| 4507730 | Memory system with automatic memory configuration A memory system includes a plurality of memory controllers which connect to a common bus. Each memory controller includes reconfiguration apparatus which enables the controller when faulty to be switched off line and another controller to be substituted i... | 03/26/1985 |
| 4506207 | Step motor driving circuit A step motor driving circuit, wherein the motor has two pairs of magnetically coupled windings (1, 2 and 3, 4) and includes switching transistors (9, 10, 11, 12) associated to the windings, diodes (15, 16, 17, 18) in parallel to the switching transistors ... | 03/19/1985 |
| 4504162 | Serial printer provided with cutter Serial printer provided with cutter, the printer being of the type in which printing is performed by a printing head mounted on a carriage sliding on guides parallel to the printing line and a continuous printing support moves perpendicularly to the direc... | 03/12/1985 |
| 4504830 | Display apparatus for facilitating maintenance of computer equipment The apparatus displays information in a manner which permits viewing at convenient operator locations. It connects to a selected number of points within the computer printed circuit boards of the equipment. The apparatus includes light emitting diode circ... | 03/12/1985 |
| 4503495 | Data processing system common bus utilization detection logic A common bus utilization detection logic that is used when a particular device connected to a common bus has been granted access to the common bus wherein bus access is granted on a priority basis. By positioning the bus utilization logic in priority posi... | 03/05/1985 |
| 4501054 | Hand tool for installing compression rings on radial positioning devices A hand held tool for installing compression rings includes a pair of relatively reciprocable coaxial cylindrical independently spring biased elements housed within a cylindrical handle which includes mode control means automatically preconditioned for ena... | 02/26/1985 |
| 4502039 | Keyboard coding apparatus Keyboard coding apparatus couples to a plurality of keys and comprises a scanning interface including a counter (23), a decoder (13) and a multiplexer (22). The scanning interface, in response to each pulse received from a microprocessor (1) through an in... | 02/26/1985 |
| 4495571 | Data processing system having synchronous bus wait/retry cycle A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O inst... | 01/22/1985 |
| 4493524 | Factory data collection terminal conduit enclosure In a computer factory data collection terminal an electrical conduit enclosure for permitting wiring to be brought up through the conduit to the factory data collection terminal and for providing full wiring protection while still permitting the terminal ... | 01/15/1985 |
| 4494186 | Automatic data steering and data formatting mechanism In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus or for transferring information via a communication channel to other data processing systems during asynchronously ge... | 01/15/1985 |
| 4493036 | Priority resolver having dynamically adjustable priority levels A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to pre... | 01/08/1985 |
| 4491908 | Microprogrammed control of extended integer and commercial instruction processor instructions through use of a data type field in a central processor unit A data processing system includes a microprogram controlled central processing unit that executes instructions. The instruction words include a data type field for identifying the type of operand processed during the execution of the instruction. The data... | 01/01/1985 |
| 4489380 | Write protected memory An interactive terminal includes a central processor unit (CPU) having a microprocessor and a random access memory (RAM). Signals from the microprocessor place the RAM in a write protect mode. If the RAM receives a write instruction from the microprocesso... | 12/18/1984 |
| 4488227 | Program counter stacking method and apparatus for nested subroutines and interrupts A computer system which facilitates the execution of nested subroutines and interrupts is disclosed. As each branch transfer within the program is executed by a control area logic, a microcommand initiates the transfer of the return address, which has bee... | 12/11/1984 |
