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| Number | Title | Issue Date |
| 7821785 | Heatsinks and a spring in a baffle slot between adjacent components A baffle has a slot, with the slot positioned between first and second adjacent components when the baffle is installed above the components. A pair of heatsinks are inserted into the slot, with at least one heatsink having a heat dissipating portion that remains ab... | 10/26/2010 |
| 6957353 | System and method for providing minimal power-consuming redundant computing hardware for distributed services A system and method to intelligently control power consumption of distributed services using a computer system that provides independent computing elements each capable of entering a power saving mode. The first algorithm is a reduced load power saving algorithm. As... | 10/18/2005 |
| 6940726 | Housing assembly having simplified circuit board assembly, retention, and electrical connection features An assembly comprising a housing and a circuit board is designed to facilitate a simplified method of assembling the circuit board into the housing, along with a simplified method of coupling the signals on the circuit board to other circuits. The circuit board is g... | 09/06/2005 |
| 6938071 | Fault tolerant storage system having an interconnection fabric that also carries network traffic A networked system includes a fault tolerant storage system (FTSS) having an interconnection fabric that also carries network traffic. A plurality of servers are coupled to an FTSS via an FTSS interconnection fabric. As soon as a packet is received from a sending no... | 08/30/2005 |
| 6928520 | Memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent Embodiments of the present invention include a memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent. The memory controller includes at least one memory-controller agent, an incoming memory... | 08/09/2005 |
| 6889244 | Method and apparatus for passing messages using a fault tolerant storage system A method and apparatus pass messages between server and client applications using a fault tolerant storage system (FTSS). The interconnection fabric that couples the FTSS to the computer systems that host the client and server applications may also be used to carry ... | 05/03/2005 |
| 6813627 | Method and apparatus for performing integer multiply operations using primitive multi-media operations that operate on smaller operands Integer multiply operations using data stored in an integer register file are performed using multi-media primitive instructions that operate on smaller operands. The present invention performs a multiply operation on a 32-bit or 64-bit value by performing multiply ... | 11/02/2004 |
| 6799263 | Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted A method for prefetching instructions into cache memory using a prefetch instruction. The prefetch instruction contains a target field, a count field, a cache level field, a flush field, and a trace field. The target field specifies the address at which prefetching ... | 09/28/2004 |
| 6792550 | Method and apparatus for providing continued operation of a multiprocessor computer system after detecting impairment of a processor cooling device A multiprocessor computer system continues operation after the failure of a cooling device coupled to a central processing unit (CPU). In accordance with the present invention, an impending failure of a cooling device is detected, and all user and operating system p... | 09/14/2004 |
| 6647618 | Method of assembling a circuit board into a housing A method of assembling a circuit board into a housing to form an assembly is disclosed. The method includes inserting a first end of the circuit board into a first slot of the housing, flexing the circuit board over a deflection/retention feature, inserti... | 11/18/2003 |
| 6598140 | Memory controller having separate agents that process memory transactions in parallel A memory controller has separate memory controller agents that process memory transactions in parallel. A memory controller in accordance with the present invention includes a plurality of memory controller agents, which are coupled to each other via a se... | 07/22/2003 |
| 6556501 | Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impendance state during write operations A multi-port computer register file has shared word lines for read and write ports and storage elements that power down during write operations. Assume that a register file in accordance with the present invention has R read ports and W write ports, and R... | 04/29/2003 |
| 6532151 | Method and apparatus for clearing obstructions from computer system cooling fans An obstruction is removed from a computer system cooling fan by manipulating fan rotation. When a fan obstruction is detected, the fan is stopped. If the obstruction is caused by an object that was drawn toward the fan intake, such as a sheet of paper, th... | 03/11/2003 |
| 6490654 | Method and apparatus for replacing cache lines in a cache memory A cache memory replacement algorithm replaces cache lines based on the likelihood that cache lines will not be needed soon. A cache memory in accordance with the present invention includes a plurality of cache lines that are accessed associatively, with a... | 12/03/2002 |
| 6472927 | Circuit having increased noise immunity and capable of generating a reference voltage or terminating a transmission line A voltage divider suppresses noise in a voltage divider output by filtering the voltages at the gate terminals of the transistors that comprise a voltage divider. In one embodiment of the present invention, a voltage divider includes a PFET transistor cou... | 10/29/2002 |
| 6434636 | Method and apparatus for performing high bandwidth low latency programmed I/O writes by passing tokens A method and apparatus performs high bandwidth low latency programmed I/O (PIO) write operations by passing tokens. A computer system in accordance with the present invention includes a plurality of CPUs, with each CPU coupled to a CPU agent. Each CPU age... | 08/13/2002 |
| 6428349 | Method and apparatus for jumpering resistors and other components on a printed circuit board A conductive clip is placed over a component mounted to a printed circuit board (PCB) to form a conductive path between terminals of the component. In one embodiment, a conductive clip is placed over a surface mount technology (SMT) component, with the cl... | 08/06/2002 |
| 6408373 | Method and apparatus for pre-validating regions in a virtual addressing scheme A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entri... | 06/18/2002 |
| 6405286 | Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes A method and apparatus determines interleaving schemes in a computer system that supports multiple interleaving schemes. In one embodiment, a memory interleaving scheme lookup table is used to assign memory interleaving schemes based on the number of avai... | 06/11/2002 |
| 6392442 | Driver circuit that compensates for skin effect losses A driver circuit compensates for skin effect losses in a transmission line by using a lower impedance when data switches at the maximum switching rate, and using a higher output impedance when data switches at less than the maximum switching rate. As is k... | 05/21/2002 |
| 6381615 | Method and apparatus for translating virtual path file access operations to physical file path access A method and apparatus virtualizes file access operations and other I/O operations in operating systems by performing string substitutions upon a file paths or other resource identifiers to convert the virtual destination of an I/O operation to a physical... | 04/30/2002 |
| 6327159 | Wireform bracket for managing computer cables A wireform bracket provides a simple, elegant, low-cost solution for managing a large number of cables, while also allowing ample airflow at the back of a computer system. A wireform bracket in accordance with the present invention includes a plurality of... | 12/04/2001 |
| 6308261 | Computer system having an instruction for probing memory latency A computer system includes a data structure that maintains availability status for registers of a processor of the computer system, wherein the availability status indicates whether an instruction attempting to read a particular register will stall. The c... | 10/23/2001 |
| 6304456 | Housing assembly having simplified circuit board assembly, retention, and electrical connection features An assembly comprising a housing and a circuit board is designed to facilitate a simplified method of assembling the circuit board into the housing, along with a simplified method of coupling the signals on the circuit board to other circuits. The circuit... | 10/16/2001 |
| 6289023 | Hardware checksum assist for network protocol stacks A fly-by checksum is generated at a lower layer of the protocol stack and travels up to a high layer of a protocol stack to verify incoming data. In one embodiment, a network adapter comprises includes one or more protocol stacks and a LAN controller that... | 09/11/2001 |
| 6279126 | Method for verifying that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically A method verifies that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically. In accordance with the present invention, a test suite written and compiled in big endian mode is loaded into memory. The tes... | 08/21/2001 |
| 6276769 | Inner window for a bezel or housing assembly A window is attached to a bezel, housing, or other assembly. The bezel, housing, or other assembly has a series of pins surrounding an opening, and the window has a corresponding series of holes. The centers of the holes are slightly off-center from the c... | 08/21/2001 |
| 6263403 | Method and apparatus for linking translation lookaside buffer purge operations to cache coherency transactions A method and apparatus link translation lookaside buffer (TLB) purge operations to cache coherency transactions, thereby allowing the TLB purge operations to be performed by hardware without significant software intervention. Computer systems having cache... | 07/17/2001 |
| 6247058 | Method and apparatus for processing network packets using time stamps A network device receives packets from a first network segment, time stamps the packets as they arrive, and transmits the packets to a second network segment. By time stamping packets as they arrive, stale packets can be identified and discarded. A stale ... | 06/12/2001 |
| 6247137 | Delaying clock and data signals to force synchronous operation in digital systems that determine phase relationships between clocks with related frequencies A method and apparatus forces synchronous operation in a system that determines a phase-based relationship between two clocks by providing selectable delays of clock and data signals. A sending IC transmits data to the receiving IC over a data bus, and pr... | 06/12/2001 |
| 6240523 | Method and apparatus for automatically determining the phase relationship between two clocks generated from the same source A method and apparatus automatically determines a phase-based relationship between two clocks generated from the same source. In accordance with the present invention, a clock generator provides a clock signal to a sending IC and a receiving IC. The sendi... | 05/29/2001 |
| 6230248 | Method and apparatus for pre-validating regions in a virtual addressing scheme A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entri... | 05/08/2001 |
| 6205545 | Method and apparatus for using static branch predictions hints with dynamically translated code traces to improve performance A run-time optimization strategy uses a trace picker to identify traces of program code in a native code pool, and a translator to translate the traces into a code cache where the traces are executed natively. Static branch prediction hints are encoded in... | 03/20/2001 |
| 6195650 | Method and apparatus for virtualizing file access operations and other I/O operations A method and apparatus virtualizes file access operations and other I/O operations in operating systems by performing string substitutions upon a file paths or other resource identifiers to convert the virtual destination of an I/O operation to a physical... | 02/27/2001 |
| 6188633 | Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impedance state during write operations A multi-port computer register file has shared word lines for read and write ports and storage elements that power down during write operations. Assume that a register file in accordance with the present invention has R read ports and W write ports, and R... | 02/13/2001 |
| 6156972 | Inner bezel for a computer chassis A bezel attaches to a chassis via pins that register the alignment of the bezel with respect to the chassis, and snap latches that retain the bezel to the chassis. The bezel of the present invention has one or more molded pins and one or more snap latches... | 12/05/2000 |
| 6153946 | Method and apparatus for providing redundant power by connecting power supplies into a segment or ring A method and apparatus provide redundant power by connecting power supplies in a segment or ring. In a first embodiment, a redundant power supply is provided at the "top" of a redundant power segment, with one or more computer devices coupled "beneath" th... | 11/28/2000 |
| 6115809 | Compiling strong and weak branching behavior instruction blocks to separate caches for dynamic and static prediction A method and apparatus varies branch prediction strategy associated with branch instructions in a trace of program code. The present invention first profiles branch instructions within a trace to record branching behavior. Next, the present invention part... | 09/05/2000 |
| 6108745 | Fast and compact address bit routing scheme that supports various DRAM bank sizes and multiple interleaving schemes An address routing scheme supports a variety of memory sizes and interleaving schemes. In one embodiment, any address bit provided by the processor can be routed to any bank, row, or column bit, and can be used to generate any rank bit. This embodiment su... | 08/22/2000 |
| 6070187 | Method and apparatus for configuring a network node to be its own gateway A configuration agent allows a network node seeking to be automatically configured with an IP address and a default gateway address to be configured as its own gateway. In first and second embodiments of the present invention, the configuration agent resi... | 05/30/2000 |
