Pike; Rosemary L.S. - US Patent Attorneys and Agents

Attorney: Pike; Rosemary L.S.

Number of patents: 40
Last date: May 08, 2012

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Number	Title	Issue Date
8174885	High speed operation method for twin MONOS metal bit array The present invention provides a novel read method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the...	05/08/2012
8056308	Apparatus and method for cutting and harvesting infestations of aquatic vegetation and/or skimming algae/floating vegetation A harvester and method for harvesting aquatic algae or floating vegetation in shallow areas of water bodies, such as lakes. The harvester is manually operated. The harvester includes a pair of blades which are manually moved by a rope connected to an extension sprin...	11/15/2011
8056213	Method to make PMR head with integrated side shield (ISS) A PMR head comprises a substrate, a magnetic pole formed over the substrate, the pole having a pole tip having a cross-sectional tapered shape wherein the pole tip is surrounded by a write gap layer, an integrated shield comprising side shields on the substrate late...	11/15/2011
7420276	Post passivation structure for semiconductor chip or wafer The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used...	09/02/2008
7416971	Top layers of metal for integrated circuits The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used...	08/26/2008
7381642	Top layers of metal for integrated circuits The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used...	06/03/2008
7359250	Twin insulator charge storage device operation and its fabrication method The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the pro...	04/15/2008
7351650	Post passivation interconnection schemes on top of the IC chips A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over...	04/01/2008
7294871	Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an ...	11/13/2007
7291551	Sub-milliohm on-chip interconnection A method to form a very low resistivity interconnection in the manufacture of an integrated circuit device is achieved. A bottom conductive layer is formed overlying a substrate. The bottom conductive layer creates a first electrical coupling of a first location and...	11/06/2007
7170132	Twin insulator charge storage device operation and its fabrication method The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the pro...	01/30/2007
6998682	Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific location...	02/14/2006
6949765	Padless structure design for easy identification of bridging defects in lines by passive voltage contrast A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles compr...	09/27/2005
6927104	Method of forming double-gated silicon-on-insulator (SOI) transistors with corner rounding A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patt...	08/09/2005
6924180	Method of forming a pocket implant region after formation of composite insulator spacers A process for forming a MOSFET device featuring a pocket region placed adjacent to only a top portion of the sides of a heavily doped source/drain region, has been developed. The process features forming a heavily doped source/drain region in an area of a semiconduc...	08/02/2005
6909273	Zero-temperature-gradient zero-bias thermally stimulated current technique to characterize defects in semiconductors or insulators A process for characterizing defects in semiconductors or insulators using a zero-bias thermally stimulated current technique wherein parasitic current is eliminated by the use of a novel ZBTSC apparatus that eliminates temperature gradient across a sample is descri...	06/21/2005
6900098	Twin insulator charge storage device operation and its fabrication method The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the pro...	05/31/2005
6879287	Packaged integrated antenna for circular and linear polarizations A high radiation efficiency antenna system in a package is achieved by the provision of a Dielectric Resonator Package. A Dielectric resonator package comprises a dielectric body of the package forming a dielectric resonator that resonates at radio frequency and a f...	04/12/2005
6869870	High performance system-on-chip discrete components using post passivation process A system and method for forming post passivation discrete components, is described. High quality discrete components are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer. ...	03/22/2005
6869884	Process to reduce substrate effects by forming channels under inductor devices and around analog blocks A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are fo...	03/22/2005
6861317	Method of making direct contact on gate by using dielectric stop layer A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with...	03/01/2005
6862223	MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can...	03/01/2005
6852605	Method of forming an inductor with continuous metal deposition A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal...	02/08/2005
6846899	Poly(arylene ether) dielectrics The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and mono...	01/25/2005
6842078	Ring oscillator with variable loading A ring oscillator circuit device is achieved. The device comprises an odd number of inverting stages. Each inverting stage has an input terminal and an output terminal. The inverter stages are coupled in a ring such that the output terminals of preceding inverting s...	01/11/2005
6830966	Fully silicided NMOS device for electrostatic discharge protection A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailori...	12/14/2004
6822268	Two layer mirror for LCD-on-silicon products and method of fabrication thereof A method of fabricating an LCD-on-silicon pixel device, comprising the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. T...	11/23/2004
6815239	Photolithographic methods for making liquid-crystal-on-silicon displays with alignment posts and optical interference layers Five new methods for the formation of an improved liquid-crystal-on-silicon display are described, in which the device structure is enhanced by the photolithographic building of alignment posts among the mirror pixels of the micro-display. These five methods accommo...	11/09/2004
6814812	Double acting cold trap A double acting cold trap equipped with a set of exhaust gas condensing fins and a set of exhaust gas condensing plates is disclosed. The invention also discloses a double acting cold trap that incorporates a deflecting plate to direct the exhaust gases over the con...	11/09/2004
6803314	Double-layered low dielectric constant dielectric dual damascene method A double layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first organic dielectric layer is deposited overlying the insulating l...	10/12/2004
6804149	Nonvolatile memory cell, operating method of the same and nonvolatile memory array The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programmi...	10/12/2004
6753260	Composite etching stop in semiconductor process integration A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOC, and SiOCN. A TEOS oxide laye...	06/22/2004
6743291	Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth A process of fabricating a CMOS device comprised with super-steep retrograde (SSR), twin well regions, has been developed. The process features the use of two, selective epitaxial growth (SEG), procedures, with the first SEG procedure resulting in the growth of bott...	06/01/2004
6731534	Bit line tracking scheme with cell current variation and substrate noise consideration for SRAM devices Described are a method and device for tracking memory cell currents using a tracking memory cell circuit wherein the challenges resulting from current degradation and process variations are eliminated. A special strap cell is provided to eliminate ground bounce phas...	05/04/2004
6709912	Dual Si-Ge polysilicon gate with different Ge concentrations for CMOS device optimization A method for forming a dual Si—Ge poly-gates having different Ge concentrations is described. An NMOS active area and a PMOS active area are provided on a semiconductor substrate separated by an isolation region. A gate oxide layer is grown overlying the semicondu...	03/23/2004
6706577	Formation of dual gate oxide by two-step wet oxidation A method of simultaneously forming differential gate oxide for both high and low voltage transistors using a two-step wet oxidation process is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas...	03/16/2004
6656643	Method of extreme ultraviolet mask engineering An EUV photolithographic mask device and a method of fabricating the same. The EUV photolithographic mask comprises a multi-layer over an EUV masking substrate and a patterned light absorbing layer formed on the multi-layer. The method comprises the steps...	12/02/2003
6624040	Self-integrated vertical MIM capacitor in the dual damascene process A method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper dual damascene process is described. A first dual damascene opening and a pair of second dual damascene openings are provided in a first dielectri...	09/23/2003
6613652	Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating laye...	09/02/2003
6610604	Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si3 N4 or an SiO2 /Si3 N4 stack gate dielectric layer. A gate material layer is formed over...	08/26/2003

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Attorney: Pike; Rosemary L.S.