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| Number | Title | Issue Date |
| 8130067 | High frequency semiconductor transformer A semiconductor transformer provides high frequency operation by forming the primary windings of the transformer around a section of magnetic material that has a hard axis that lies substantially parallel to the direction of the magnetic field generated by the prima... | 03/06/2012 |
| 8057246 | Compact multiport test jack A multiport test jack that supports the testing of a number of individual telephone lines in an interface device, such as a network interface device or an optical line terminal, has a physical structure that is smaller in size than the size of a corresponding number... | 11/15/2011 |
| 8056246 | Ferrofluidic orientation sensor and method of forming the sensor An orientation sensor includes a measure of ferrofluid that moves as the orientation sensor moves. The movement of the ferrofluid, which lies over a number of coils, alters the magnetic permeability of the flux path around each coil. The orientation sensor determine... | 11/15/2011 |
| 8048704 | Method of forming a MEMS topped integrated circuit with a stress relief layer The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer an... | 11/01/2011 |
| 8044755 | MEMS power inductor A scalable MEMS inductor is formed on the top surface of a semiconductor die. The MEMS inductor includes a plurality of magnetic lower laminations, a circular trace that lies over and spaced apart from the magnetic lower laminations, and a plurality of upper laminat... | 10/25/2011 |
| 8030733 | Copper-compatible fuse target A copper-compatible fuse target is fabricated by forming a copper target structure at the same time that the copper traces are formed. After the copper target structure and the copper traces have been formed, a conductive target, such as an aluminum target, is forme... | 10/04/2011 |
| 8004061 | Conductive trace with reduced RF impedance resulting from the skin effect The radio frequency (RF) impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fins that extend away from the base region. When formed in a spiral configuration having a number of loops, the m... | 08/23/2011 |
| 7996805 | Method of stitching scan flipflops together to form a scan chain with a reduced wire length The scan flipflops on a semiconductor chip are stitched together to form one or more scan chains, located in one or more standard cell placement regions, after the optimal physical location of each scan flip-flop has been determined. As a result, the total length of... | 08/09/2011 |
| 7996034 | Cellular telephone handset with increased reception sensitivity and reduced transmit power levels A cellular telephone handset utilizes an electrically-steered directional antenna to increase the received signal strength when the handset is in a poor signal environment. As a result, the handset reduces the need for an end user to tilt and twirl their head to try... | 08/09/2011 |
| 7978454 | ESD structure that protects against power-on and power-off ESD event An electrostatic discharge protection circuit (ESD protection circuit) provides ESD protection to all NMOS/PMOS transistors that are connected to the pins of a CMOS integrated circuit (IC). The ESD protection circuit will protect the CMOS IC against an ESD event, re... | 07/12/2011 |
| 7964934 | Fuse target and method of forming the fuse target in a copper process flow A fuse target is fabricated in a copper process by forming a number of copper targets at the same time that the copper traces are formed. After the copper targets and the copper traces have been formed, metal targets, such as aluminum targets, are formed on the copp... | 06/21/2011 |
| 7919807 | Non-volatile memory cell with heating element The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The progr... | 04/05/2011 |
| 7902946 | MEMS relay with a flux path that is decoupled from an electrical path through the switch and a suspension structure that is independent of the core structure and a method of forming the same A micro-electromechanical (MEMS) relay decouples a flux path from magnetic actuation from the electrical path through the switch to eliminate signal degradations that result from fluctuations in the current around the core and, thereby the flux. In addition, the MEM... | 03/08/2011 |
| 7902013 | Method of forming a semiconductor die with reduced RF attenuation An electrically floating region is formed in the top surface of a semiconductor wafer to implement a radio frequency (RF) blocking structure. The RF blocking structure lies below the metal pads and traces that carry an RF signal in a metal interconnect structure to ... | 03/08/2011 |
| 7848562 | Method of reducing the time required to perform a passive voltage contrast test The time required to perform a passive voltage contrast test of an area of interest of a layer of interest is substantially reduced by digitizing a passive voltage contrast image to form contrast data that represents the image, and comparing the contrast data to com... | 12/07/2010 |
| 7847385 | Stacked die structure with an underlying copper-topped die A copper-topped die, which has exposed copper lines and pads, is utilized as the lower die in a stacked die structure. A non-conductive material is formed over the lower copper-topped die, and then selectively removed so that the non-conductive material covers and l... | 12/07/2010 |
| 7863962 | High voltage CMOS output buffer constructed from low voltage CMOS transistors A high voltage CMOS output buffer is constructed from low voltage CMOS transistors. The output buffer employs a series of unique CMOS inverter stages, each of which contains a switched PMOS transistor, one or more voltage drop blocks, and a switched NMOS transistor.... | 01/04/2011 |
| 7863644 | Bipolar transistor and method of forming the bipolar transistor with a backside contact NPN and PNP bipolar junction transistors are formed on a wafer in a fabrication process that eliminates the heavily-doped buried layers and the lightly-doped epitaxial layer by forming back side collector contacts that are electrically connected to an interconnect s... | 01/04/2011 |
| 7790602 | Method of forming a metal interconnect with capacitive structures that adjust the capacitance of the interconnect A method of forming capacitive structures in trenches which have been formed in a multilevel metal interconnect structure is disclosed. The method of forming the capacitive structures allows the capacitance of the multilevel metal interconnect structure to be adjust... | 09/07/2010 |
| 7764517 | Power supply with reduced power consumption when a load is disconnected from the power supply Detection and control circuitry are added to a conventional power supply to detect when a load, such as a portable electronic device, has been disconnected from the power supply and, when disconnected, interrupt a current path to the primary windings of a transforme... | 07/27/2010 |
| 7754986 | Mechanical switch that reduces the effect of contact resistance A switch structure substantially reduces the effect of contact resistance by placing two mechanical switches in parallel between a source and a load, and sequentially closing and opening the mechanical switches so that one switch closes before the other switch, and ... | 07/13/2010 |
| 7754540 | Method of forming a SiGe DIAC ESD protection structure A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pa... | 07/13/2010 |
| 7754505 | Method of forming a silicon-based light-emitting structure A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and em... | 07/13/2010 |
| 7754502 | Backside defect detector and method that determines whether unwanted materials are present on the backside of a semiconductor wafer Minute materials which can be undesirably left on the backside of a semiconductor wafer are detected by scanning the semiconductor wafer with an infra-red (IR) light following the completion of a process step that forms and then selectively removes a material from t... | 07/13/2010 |
| 7724169 | Semiconductor chip with a number of A/D converters that include a group of redundant A/D converters The manufacturing yield of an A/D converter semiconductor chip is significantly increased by utilizing a number of A/D converter circuits that include a group of redundant A/D converter circuits. As a result, the semiconductor chip can be wired to form a “good” ... | 05/25/2010 |
| 7723792 | Floating diodes A semiconductor chip is ESD protected, in part, by utilizing floating lateral clamp diodes. Unlike conventional clamp diodes, which are based upon parasitic bipolar devices associated with large MOS transistors, the floating lateral clamp diodes utilize a well forme... | 05/25/2010 |
| 7719114 | Edit structure that allows the input of a logic gate to be changed by modifying any one of the metal or via masks used to form the metal interconnect structure An edit structure is disclosed that allows the input of a logic gate to be changed by modifying any one of the metal and via masks that are used to form the metal interconnect structure. As a result, a first permanent logic state provided by a tie-in circuit can be ... | 05/18/2010 |
| 7718448 | Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays A number of modified lateral DMOS (LDMOS) transistor arrays are formed and tested to determine if a measured value, such as a series on-resistance, substrate current, breakdown voltage, and reliability, satisfies process alignment requirements. The modified LDMOS tr... | 05/18/2010 |
| 7709956 | Copper-topped interconnect structure that has thin and thick copper traces and method of forming the copper-topped interconnect structure A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that... | 05/04/2010 |
| 7705421 | Semiconductor die with an integrated inductor An integrated circuit inductor has a number of vertical metal segments, a number of lower metal straps that electrically connect alternate metal segments, and a number of upper metal straps that electrically connect alternate metal segments to form a continuous elec... | 04/27/2010 |
| 7705411 | MEMS-topped integrated circuit with a stress relief layer The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer an... | 04/27/2010 |
| 7701754 | Multi-state electromechanical memory cell An electromechanical memory cell utilizes a cantilever and a laterally positioned electrode. The cantilever is spaced apart from the electrode by a distance that is greater than the elastic limit of the cantilever. The memory cell is programmed by applying voltages ... | 04/20/2010 |
| 7676922 | Method of forming a saucer-shaped half-loop MEMS inductor with very low resistance A micro-electromechanical system (MEMS) inductor is formed in a saucer shape that completely surrounds a magnetic core structure which is formed from a ferromagnetic material. In addition, an array of MEMS inductors can be formed by dividing up the saucer-shaped MEM... | 03/16/2010 |
| 7667204 | Low-power positron emission tomography (PET) imaging system The power consumed by a positron emission tomography (PET) imaging system is substantially reduced by utilizing an analog memory, such as a switch-capacitor analog memory, to sample and store analog values for a number of gamma ray signals so that only the stored an... | 02/23/2010 |
| 7647571 | Method of identifying state nodes at the transistor level in a sequential digital circuit The state nodes in a sequential digital circuit are identified by identifying the minimal combinatorial feedback loops that are present in the digital circuit. Each minimal combinatorial feedback loop has at least one driver node, and one driver node from each minim... | 01/12/2010 |
| 7646064 | Semiconductor die with aluminum-spiked heat pipes A low thermal pathway is provided from the top surface of a silicon substrate to the bottom surface of the silicon substrate by first forming aluminum plugs in the bottom surface of the silicon substrate that contact the silicon substrate and extend up towards the t... | 01/12/2010 |
| 7645657 | MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradation A MOS transistor is formed with a dual-layer silicon oxynitride (SiON) etch stop film that protects the transistor from plasma induced damage (PID) and hot carrier degradation, thereby improving the reliability of the transistors. The first SiON layer is formed with... | 01/12/2010 |
| 7644490 | Method of forming a microelectromechanical (MEMS) device A method of forming an actuator and a relay using a micro-electromechanical (MEMS)-based process is disclosed. The method first forms the lower sections of a square copper coil, and then forms an actuation member that includes a core section and a horizontally adjac... | 01/12/2010 |
| 7642116 | Method of forming a photodiode that reduces the effects of surface recombination sites The loss of photogenerated electrons to surface electron-hole recombination sites is minimized by utilizing a first p-type surface region to form a depletion region that functions as a first barrier that repels photogenerated electrons from the surface recombination... | 01/05/2010 |
| 7633870 | Network forwarding device and method that forward timing packets through the device with a constant delay The variable latency associated with standard network forwarding devices is eliminated by forwarding timing packets through a network forwarding device with a constant delay. The network forwarding device of the invention time stamps timing packets that are received... | 12/15/2009 |
