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| Number | Title | Issue Date |
| 7355968 | Method of stateless group communication and repair of data packets transmission to nodes in a distribution tree Disclosed is a method for stateless group communication based on constructing and encoding sender based trees. The headers obtained by encoding the distribution trees are inserted in each communication packet. The encoding allows partial or full decoding of the dist... | 04/08/2008 |
| 7339963 | High speed data channel including a CMOS VCSEL driver and a high performance photodetector and CMOS photoreceiver A high speed optical channel including an optical driver and a photodetector in a CMOS photoreceiver. The optical channel driver includes a FET driver circuit driving a passive element (e.g., an integrated loop inductor) and a vertical cavity surface emitting laser ... | 03/04/2008 |
| 7336100 | Single supply level converter A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input sign... | 02/26/2008 |
| 7318126 | Asynchronous symmetric multiprocessing An apparatus for serializing concurrent requests to multiple processors includes a signal merging tree structure and a traversal mechanism. The tree structure has a root node and leaf nodes for connecting a data consumer to the root. The tree structure serializes co... | 01/08/2008 |
| 7318074 | System and method for achieving deferred invalidation consistency In a system having a plurality of caches, a method for maintaining cached objects includes storing an object in a plurality of caches. In response to a request to update the object, a future invalidation time is determined when the object should be invalidated in ca... | 01/08/2008 |
| 7313554 | System and method for indexing queries, rules and subscriptions This invention introduces a new concept called virtual construct intervals (VCI), where each predicate interval is decomposed into one or more of these construct intervals. These VCIs strictly cover the predicate interval. Namely, every attribute value covered by th... | 12/25/2007 |
| 7308593 | Interlocked synchronous pipeline clock gating An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with ... | 12/11/2007 |
| 7295457 | Integrated circuit chip with improved array stability A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs ... | 11/13/2007 |
| 7289369 | DRAM hierarchical data path A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local bit line (LBL) in each segment. Each LBL drives a sense device that d... | 10/30/2007 |
| 7285480 | Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FE... | 10/23/2007 |
| 7274217 | High performance PFET header in hybrid orientation technology for leakage reduction in digital CMOS VLSI designs Discloses are CMOS circuit designs that combine MTCMOS and hybrid orientation technology to achieve the dual objectives of high performance and low standby leakage power. The invention utilizes novel combinations of a thick-oxide high-VTH PFET header with various ga... | 09/25/2007 |
| 7272264 | System and method for hole filling in 3D models A method for hole-filling in 3D models includes identifying vertices adjacent to hole boundaries in a mesh of points on a digital image and constructing a signed distance function based on vertices adjacent to hole boundaries. A Radial Basis Function is fit based on... | 09/18/2007 |
| 7269645 | Seamless migration of one or more business processes and their work environment between computing devices and a network A mechanism for end-to-end mobile e-business applications for migration of business processes and business context between two or more clients and servers to provide transparency and reliability given unreliable networks and systems is disclosed. The e-business appl... | 09/11/2007 |
| 7237217 | Resonant tree driven clock distribution grid An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated ci... | 06/26/2007 |
| 7232745 | Body capacitor for SOI memory description A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between th... | 06/19/2007 |
| 7212992 | Method and system for tracking a deposit The present invention relates to tracking the use, transfer, impact and/or effect of a deposit. An index is correlated to a depositor making a deposit. The deposit, or portion thereof, and the index are transferred to one or more destinations. The deposit, or portio... | 05/01/2007 |
| 7180818 | High performance register file with bootstrapped storage supply and method of reading data therefrom A multi-port register file, integrated circuit (IC) chip including one or more multi-port register files and method of reading data from the multi-port register file. The supply to storage latches in multi-port register file is selectively bootstrapped above the sup... | 02/20/2007 |
| 7177177 | Back-gate controlled read SRAM cell An eight transistor static random access memory (SRAM)device includes first and second inverters, a first bit line, a first complement bit line, a pair of write access transistors, and a pair of read access transistors. Each of the first and second inverters include... | 02/13/2007 |
| 7173875 | SRAM array with improved cell stability A CMOS static random access memory (SRAM) cell array, an integrated chip including the array and a method of accessing cells in the array with improved cell stability. Bit lines connected to half selected cells in the array are floated during cell accesses for impro... | 02/06/2007 |
| 7170809 | Stable memory with high mobility cell devices A random access memory includes a logic circuit coupled to a power supply of a column having a memory cell. The logic circuit adjusts the supply voltage for the memory cell in the column in accordance with a control signal. A control circuit is coupled to the logic ... | 01/30/2007 |
| 7168009 | Method and system for identifying errors in computer software Disclosed are a method and system for analyzing a computer program. The method comprises the steps of analyzing the program to generate an initial error report and a list of suspected error conditions, and generating a set of assertions and inserting the assertions ... | 01/23/2007 |
| 7167173 | Method and structure for image-based object editing Disclosed are an image editing user interface system and method. The system includes one or more computers with one or more graphical user interfaces, and a receiving process for receiving one or more rendered two dimensional images on the computer graphical user in... | 01/23/2007 |
| 7117455 | System and method for derivative-free optimization of electrical circuits The present invention is a system and method for optimizing electrical circuits by means of derivative-free optimization. Tunable parameters such as component values, transistor sizes or model parameters are automatically adjusted to obtain an optimal circuit. Any m... | 10/03/2006 |
| 7111260 | System and method for incremental statistical timing analysis of digital circuits The present invention is a system and method for efficiently and incrementally updating the statistical timing of a digital circuit after a change has been made in the circuit. One or more changes in the circuit is/are followed by timing queries that are answered ef... | 09/19/2006 |
| 6832201 | Method and system for optimizing request shipping in workflow management systems A method for optimizing request shipping within a plurality of distributed networked computer systems holding a distributed application the usage of which realizes a process model underlying said application is proposed in which said process model comprises a busine... | 12/14/2004 |
| 6798780 | Techniques for achieving high responsiveness from communicating nodes, and verifying, measuring and deterring any unresponsiveness thereof Techniques for establishing contact between a first node and a second node in a communication system having a plurality of nodes. Upon a failure of an attempt by the first node to contact the second node, the first node contacts a 3rd party node, which in turn attem... | 09/28/2004 |
