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A method of swing on a swing is disclosed, in which a user positioned on a standard swing suspended by two chains from a substantially horizontal tree branch induces side to side motion by pulling alternately on one chain and then the other.
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| Number | Title | Issue Date |
| 8183642 | Gate effective-workfunction modification for CMOS CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control lay... | 05/22/2012 |
| 8178430 | N-type carrier enhancement in semiconductors A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implan... | 05/15/2012 |
| 8174990 | Mechanism and system for programmable measurement of aggregate metrics from a dynamic set of nodes A method for measuring performance of system. The method includes the steps of retrieving a metric definition from a declarative metrics specification, obtaining a list of computing nodes from a database that are currently assigned to the metric definition, obtainin... | 05/08/2012 |
| 8164128 | Magnetic devices and techniques for formation thereof Techniques for forming a magnetic device are provided. In one aspect, a magnetic device includes a magnetic tunnel junction and a dielectric layer formed over at least a portion of the magnetic tunnel junction. The dielectric layer is configured to have an underlaye... | 04/24/2012 |
| 8158449 | Particle emission analysis for semiconductor fabrication steps A structure and a method for operating the same. The method includes providing a detecting structure which includes N detectors. N is a positive integer. A fabrication step is simultaneously performed on the detecting structure and M product structures in a fabricat... | 04/17/2012 |
| 8140681 | Decentralized application placement for web application middleware A decentralized process to ensure the dynamic placement of applications on servers under two types of simultaneous resource requirements, those that are dependent on the loads placed on the applications and those that are independent. The demand (load) for applicati... | 03/20/2012 |
| 8140666 | Method and apparatus for network distribution and provisioning of applications across multiple domains Techniques are disclosed for network distribution and provisioning of applications, such as transactional applications and parallel applications, across multiple administrative domains that ensure compliance with service level agreements. For example, a method of pr... | 03/20/2012 |
| 8138543 | Hybrid FinFET/planar SOI FETs A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the pla... | 03/20/2012 |
| 8138410 | Optical tandem photovoltaic cell panels A solar energy conversion device comprises a vertical stack of at least two panels stacked in a hierarchy from an upper panel to a lower panel with each of the panels including a matching array of solar cells having a different energy bandgap from other panels of so... | 03/20/2012 |
| 8137107 | Knowledge management for recursively virtualized teams A method, system, and computer program for interacting with team members of a virtual team. Persistent storage is configured to store collective qualifications of the virtual team based on the individual qualifications of the team members, while a team broker is con... | 03/20/2012 |
| 8126756 | Method and system for real time measurement data adjudication and service level evaluation A method and system for adjudicating measurement data in real time and re-adjudicating a segment of an input measurement data stream upon submission of a new adjudication instruction in a service level evaluation system. An adjudication instruction associated with a... | 02/28/2012 |
| 8126753 | Evaluation of a process metric An exemplary method of responding to a request for a value of at least one metric associated with at least one process includes a step of determining whether responding to the request requires updating the value of the at least one metric. When responding to the req... | 02/28/2012 |
| 8120138 | High-Z structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the subs... | 02/21/2012 |
| 8115302 | Electronic module with carrier substrates, multiple integrated circuit (IC) chips and microchannel cooling device Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that ... | 02/14/2012 |
| 8110746 | Cooling of substrate using interposer channels A structure. The structure includes an interposer adapted to be interposed between a heat source and a heat sink and to transfer heat from the heat source to the heat sink. The interposer includes an enclosure that encloses a cavity. The enclosure is made of a therm... | 02/07/2012 |
| 8110321 | Method of manufacture of damascene reticle A method for manufacturing an optical projection reticle employs a damascene process. First feature recesses are etched into a projection reticle mask plate which is transmissive or transparent. Then feature recesses are tilled with a radiation transmissivity modify... | 02/07/2012 |
| 8103714 | Transactional quality of service in event stream processing middleware Computer implemented method, system and computer usable program code for achieving transactional quality of service in a transactional object store system. A transaction is received from a client and is executed, wherein the transaction comprises reading a read-only... | 01/24/2012 |
| 8101856 | Quantum well GaP/Si tandem photovoltaic cells Two junction solar energy conversion devices, i.e. photovoltaic cells have a bottom silicon N+/P/P+ photovoltaic cell and an upper GaP N+/P/P+ photovoltaic cell containing quantum well layers which extend the wavelength range over which the GaP cell absorbs light. T... | 01/24/2012 |
| 8080805 | FET radiation monitor A semiconductor device includes a semiconductor substrate; a buried insulator layer disposed on the semiconductor substrate, the buried insulator layer configured to retain an amount of charge in a plurality of charge traps in response to a radiation exposure by the... | 12/20/2011 |
| 8076756 | Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep I... | 12/13/2011 |
| 8059400 | Cooling of substrate using interposer channels A method of forming a structure. An interposer is provided. The interposer is adapted to be interposed between a heat source and a heat sink and to transfer heat from the heat source to the heat sink. The interposer includes an enclosure that encloses a cavity. The ... | 11/15/2011 |
| 8039966 | Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects A structure, tool and method for forming in-situ metallic/dielectric caps for interconnects. The method includes forming wire embedded in a dielectric layer on a semiconductor substrate, the wire comprising a copper core and an electrically conductive liner on sidew... | 10/18/2011 |
| 8037471 | Systems and methods for constructing relationship specifications from component interactions Techniques for automatically creating at least one relationship specification are provided. For example, one computer-implemented technique includes observing at least one interaction between two or more components of at least one distributed computing system, conso... | 10/11/2011 |
| 8037240 | System and method for using reversed backup operation for minimizing the disk spinning time and the number of spin-up operations A system and method for providing reversed backup operation for keeping local hard drives in a stand-by (non-spinning) mode thereby extending the life of local hard drives and reducing power consumption, heat and noise produced by the local drives. The present inven... | 10/11/2011 |
| 8032615 | Dynamic online multi-parameter optimization system and method for autonomic computing systems A method and system performs dynamic online multi-parameter optimization for autonomic computing systems. A simplex is maintained. The system's performance is measured for the particular setting of configuration parameters associated with each point in the simplex. ... | 10/04/2011 |
| 8030716 | Self-aligned CMOS structure with dual workfunction A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blan... | 10/04/2011 |
| 8023305 | High density planar magnetic domain wall memory apparatus A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register s... | 09/20/2011 |
| 8021949 | Method and structure for forming finFETs with multiple doping regions on a same chip A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form f... | 09/20/2011 |
| 8019816 | Method and system for mediating published message streams for selective distribution A computer implemented method, system and computer program product for delivering published messages to at least one subscriber in a publish-subscribe messaging system. A computer implemented method for delivering published messages to a subscriber includes receivin... | 09/13/2011 |
| 8009453 | High density planar magnetic domain wall memory apparatus A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register s... | 08/30/2011 |
| 8003455 | Implantation using a hardmask A method for processing CMOS wells, and performing multiple ion implantations with the use of a single hard mask is disclosed. The method includes forming and patterning a hardmask over a substrate, whereby the hardmask attains a first opening. The substrate may be ... | 08/23/2011 |
| 7975031 | Change management in multi-domain environments Method, server, and computer product are provided to implement change management across domains. Memory is included for storing a program. A processor is functionally coupled to the memory and is responsive to computer-executable instructions contained in the progra... | 07/05/2011 |
| 7971033 | Limiting entries in load issued premature part of load reorder queue searched to detect invalid retrieved values to between store safe and snoop safe pointers for the congruence class A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, including dispatching the load instructions; inserting the load instructions in the LRQ in program order; clea... | 06/28/2011 |
| 7966478 | Limiting entries in load reorder queue searched for snoop check to between snoop peril and tail pointers A method for reducing entries searched in a load reorder queue (LRQ) when snoop instructions are executed by a processor, including checking load reorder queue (LRQ) entries located between a load_peril_snoop register and a lrq_tail register for addresses matching t... | 06/21/2011 |
| 7962646 | Continuous feedback-controlled deployment of message transforms in a distributed messaging system The present invention solves the disadvantages of the prior art and provides a distributed messaging system supporting stateful subscriptions. A stateful publish-subscribe system extends the functionality of the content-based approach to include more general state-v... | 06/14/2011 |
| 7955967 | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a ... | 06/07/2011 |
| 7955955 | Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep I... | 06/07/2011 |
| 7947549 | Gate effective-workfunction modification for CMOS CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control lay... | 05/24/2011 |
| 7944006 | Metal gate electrode stabilization by alloying Stabilized metal gate electrode for complementary metal-oxide-semiconductor (“CMOS”) applications and methods of making the stabilized metal gate electrodes are disclosed. Specifically, the metal gate electrodes are stabilized by alloying wherein the alloy compr... | 05/17/2011 |
| 7939823 | Method and structures for accelerated soft-error testing An integrated circuit, method of forming the integrated circuit and a method of testing the integrated circuit for soft-error fails. The integrated circuit includes: a silicon substrate; a dielectric layer formed over the substrate; electrically conductive wires for... | 05/10/2011 |
