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...Daniel Webster invented a "bull plow" to pull out tree stumps. It didn't catch on because it was huge and required four oxen to pull it!
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| Number | Title | Issue Date |
| 7221352 | Driving method for improving display uniformity in multiplexed pixel Disclosed is an image display device to secure uniformity of a screen without luminance unevenness by reducing the number of signal lines and enhancing accuracy in voltages to be applied to respective pixels. In an interval after a scan line Gn+2 is set to selection... | 05/22/2007 |
| 7217496 | Fluorinated photoresist materials with improved etch resistant properties A photoresist composition including a polymer is disclosed, wherein the polymer includes at least one monomer having the formula: where R1 represents hydrogen (H), a linear, branched or cyclo alkyl gro... | 05/15/2007 |
| 7211446 | Method of patterning a magnetic tunnel junction stack for a magneto-resistive random access memory A method of patterning a magnetic tunnel junction (MTJ) stack is provided. According to such method, an MTJ stack is formed having a free layer, a pinned layer and a tunnel barrier layer disposed between the free layer and the pinned layer. A first area of the MTJ s... | 05/01/2007 |
| 7102916 | Method and structure for selecting anisotropy axis angle of MRAM device for reduced power consumption A method for determining a desired anisotropy axis angle for a magnetic random access memory (MRAM) device includes selecting a plurality of initial values for the anisotropy axis angle and determining, for each selected initial value, a minimum thickness for at lea... | 09/05/2006 |
| 6985384 | Spacer integration scheme in MRAM technology A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process ... | 01/10/2006 |
| 6974358 | Discrete magnets in dielectric forming metal/ceramic laminate and process thereof The present invention relates generally to a new dielectric forming metal/ceramic laminate magnet and process thereof. More particularly, the invention encompasses a new process for fabrication of a large area laminate magnet with a significant number of holes, inte... | 12/13/2005 |
| 6914320 | Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition ... | 07/05/2005 |
| 6900092 | Surface engineering to prevent epi growth on gate poly during selective epi processing The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon laye... | 05/31/2005 |
| 6893979 | Method for improved plasma nitridation of ultra thin gate dielectrics A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The in... | 05/17/2005 |
| 6893936 | Method of Forming strained SI/SIGE on insulator with silicon germanium buffer A method is disclosed for forming a semiconductor wafer having a strained Si or SiGe layer on an insulator layer. The method produces a structure having a SiGe buffer layer between the insulator layer and the strained Si or SiGe layer, but eliminates the need for Si... | 05/17/2005 |
| 6887783 | Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition ... | 05/03/2005 |
| 6876228 | Field programmable gate array It is one object of the present invention to provide an FPGA for which the configuration time and the time required for rewriting connection information and logic structure information can be reduced, and for which the size of the area occupied can also be reduced. ... | 04/05/2005 |
| 6873027 | Encapsulated energy-dissipative fuse for integrated circuits and method of making the same A laser-programmable fuse structure for an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the fuse structure includes a conductive layer, the conductive layer completing a conductive path between wiring segments in a wiring laye... | 03/29/2005 |
| 6869860 | Filling high aspect ratio isolation structures with polysilazane based material Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a ... | 03/22/2005 |
| 6865136 | Timing circuit and method of changing clock period The object of this invention is to provide a timing circuit that can change a clock period with low power consumption. The timing circuit includes a clock generator 11, comparators 12 and 13 for comparing an inputted control voltage TDV and refe... | 03/08/2005 |
| 6858111 | Conductive polymer interconnection configurations A method of forming an electrical connection between two devices is disclosed. In an exemplary embodiment of the invention, the method includes soldering a second solderable cap of an interconnection to a first contact pad of a first component. The interconnection f... | 02/22/2005 |
| 6849563 | Method and apparatus for controlling coating thickness The coating thickness and uniformity of spin-on deposition layers on semiconductor wafers is controlled through the in situ control of the viscosity and homogeneity of the mixture of precursor material and solvent material. The thickness of the deposited material is... | 02/01/2005 |
| 6842361 | Memory cell, memory circuit block, data writing method and data reading method An object of the present invention is to provide a memory cell, a memory circuit block, a data writing method, and a data reading method which realize a reduction in the number of metal layers, cost, and the chip size and an increase of production yields and product... | 01/11/2005 |
| 6838355 | Damascene interconnect structures including etchback for low-k dielectric materials A method for forming back-end-of-line (BEOL) interconnect structures in disclosed. The method and resulting structure includes etchback for low-k dielectric materials. Specifically, a low dielectric constant material is integrated into a dual or single damascene wir... | 01/04/2005 |
| 6825097 | Triple oxide fill for trench isolation In an integrated circuit process for SOI including trench device isolation, the problem of voids in the trench fill is addressed by a triple fill process, in which a thermal oxide sidewall having recesses at the bottom corners is covered with a LPCVD deposition that... | 11/30/2004 |
| 6816403 | Capacitively coupled sensing apparatus and method for cross point magnetic random access memory devices A method for sensing data stored within a cross point magnetic random access memory (MRAM) device includes establishing an offset voltage of a sense amplifier, the sense amplifier selectively coupled to a selected bitline within the MRAM device, the selected bitline... | 11/09/2004 |
| 6815346 | Unique feature design enabling structural integrity for advanced low k semiconductor chips A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected b... | 11/09/2004 |
| 6806138 | Integration scheme for enhancing capacitance of trench capacitors The capacitance of deep trench capacitors is enhanced by increasing the surface area of the doped region of the trench to be used for one electrode of the capacitor. After formation of the deep trench and a collar on an upper region of the trench, and after optional... | 10/19/2004 |
| 6803315 | Method for blocking implants from the gate of an electronic device via planarizing films A method is provided for blocking implants from the gate electrode of an FET device. Form a first planarizing film covering the substrate and the gate electrode stack. The first planarizing film is planarized by either polishing or self-planarizing. For deposition b... | 10/12/2004 |
| 6784091 | Maskless array protection process flow for forming interconnect vias in magnetic random access memory devices A method for forming interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. A encapsulating dielectric layer is formed over the array of MTJ stack... | 08/31/2004 |
| 6785154 | MRAM and access method thereof A magnetic random access memory (MRAM) circuit block and access method thereof are disclosed herein which includes a circuit for sensing a data write current passing through a bitline 32 and, for generating a stop signal for stopping a data write current supp... | 08/31/2004 |
| 6770144 | Multideposition SACVD reactor There is disclosed a high throughput multideposition SACVD reactor that enables the rapid thermal deposition of dielectric materials such as Si3N4, SiO2, and SiON and non-dielectric materials such as polysilicon onto a semiconductor ... | 08/03/2004 |
| 6764883 | Amorphous and polycrystalline silicon nanolaminate A method for forming a uniform layered structure comprising an ultra-thin layer of amorphous silicon and its thermal oxide is disclosed. In one aspect, a method for forming a nanolaminate of silicon oxide on a substrate is disclosed. In another aspect, a method for ... | 07/20/2004 |
| 6765634 | Liquid crystal display device and display device A color liquid crystal display device is disclosed which is capable of securing sufficient luminance while achieving a high National Television System Committee (NTSC) ratio. Specifically, a liquid crystal display device is disclosed which includes a cold cathode fl... | 07/20/2004 |
| 6764922 | Method of formation of an oxynitride shallow trench isolation An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench li... | 07/20/2004 |
| 6759282 | Method and structure for buried circuits and devices A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component ... | 07/06/2004 |
| 6754900 | System for providing web browser access to an operating system desktop A system, operable on a plurality of different computer operating systems, for providing web browser access to the operating system desktop having icons displayed on a screen thereof, wherein the desktop icons provide links to executable programs of and information ... | 06/22/2004 |
| 6749684 | Method for improving CVD film quality utilizing polysilicon getterer A method is disclosed for forming an epitaxial layer on a front side of a substrate formed of a monocrystalline material, using a chemical vapor deposition system. In this method, a plurality of gettering wafers formed of a gettering material are arranged in the CVD... | 06/15/2004 |
| 6750702 | Limiting amplifier A limiting amplifier comprises a differential amplifying stage combined with a differential output stage. The limiting amplifier is characterized in that a first and a second resistor means are coupled to the differential amplifying stage and to the differential out... | 06/15/2004 |
| 6742530 | Semi-aqueous solvent cleaning of paste processing residue from substrates A process of cleaning of objects that relate to semiconductor fabrication processes, such as, for example, conductive paste screening in the production of multilayer ceramic substrates and composite solder paste by stencil printing in electronic circuit assembly. Sp... | 06/01/2004 |
| 6743642 | Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology A method for manufacturing a magnetoresistive random access memory (MRAM) cell is disclosed, which alleviates the problem of Neel coupling caused by roughness in the interface between the tunnel junction layer and the magnetic layers. The method includes depositing ... | 06/01/2004 |
| 6737747 | Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor depositio... | 05/18/2004 |
| 6728712 | System for updating internet address changes A process and system for updating desired inter- or intra-net addresses at a client computer. There is provided a plurality of client computers, a database accessible by each of the client computers, a network server through which the client computers may access fil... | 04/27/2004 |
| 6726984 | Ceramic structure using a support sheet The present invention relates generally to a new ceramic structure and process thereof. Basically, the present invention relates to a structure and method for forming laminated structures and more particularly to a structure and method for fabricating multi-layer ce... | 04/27/2004 |
| 6716764 | Method of forming first level of metallization in DRAM chips There is disclosed a method of forming contacts and metal lands onto a semiconductor structure at the first level of metallization (M0). The initial structure is a silicon substrate having diffusion regions formed therein and a plurality of gate conductor sta... | 04/06/2004 |
