Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
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| Number | Title | Issue Date |
| 8185662 | Using end-to-end credit flow control to reduce number of virtual lanes implemented at link and switch layers A method and circuit for implementing enhanced transport layer flow control, and a design structure on which the subject circuit resides are provided. The transport layer provides multiple virtual lanes to application layers, and provides buffering and credit contro... | 05/22/2012 |
| 8170024 | Implementing pointer and stake model for frame alteration code in a network processor A method, apparatus and computer program product are provided for implementing a pointer and stake model for frame alteration code in a network processor. A current pointer and a stake are provided for a packet selected for transmit. The current pointer is maintaine... | 05/01/2012 |
| 8166357 | Implementing logic security feature for disabling integrated circuit test ports ability to scanout data A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal s... | 04/24/2012 |
| 8156501 | Implementing dynamic authority to perform tasks on a resource A method, apparatus and computer program product implement dynamic authority for a user to perform tasks on a resource. A user selected task on a resource is identified and analyzed to determine whether the task changes a state of the resource. When determined that ... | 04/10/2012 |
| 8140833 | Implementing polymorphic branch history table reconfiguration A method, apparatus and computer program product are provided for implementing polymorphic branch history table (BHT) reconfiguration. A BHT includes a plurality of predetermined configurations corresponding predetermined operational modes. A first BHT configuration... | 03/20/2012 |
| 8135934 | Dynamically allocating limited system memory for DMA among multiple adapters A method, apparatus, and computer program product dynamically allocate limited system memory for direct memory access (DMA) among a plurality of input/output (I/O) adapters in a system partition. Initially a minimum entitlement of I/O entitled memory capacity is all... | 03/13/2012 |
| 8130902 | High-resolution, active-optic X-ray fluorescence analyzer Active optics apparatus and method for aligning active optics are provided for a high-resolution, active optic fluorescence analyzer combining a large acceptance solid angle with wide energy tunability. A plurality of rows of correctors selectively controlled to ben... | 03/06/2012 |
| 8127083 | Eliminating silent store invalidation propagation in shared memory cache coherency protocols A method and circuit for eliminating silent store invalidation propagation in shared memory cache coherency protocols, and a design structure on which the subject circuit resides are provided. A received data value is compared with a stored cache data value. When th... | 02/28/2012 |
| 8106360 | Microscopic infrared analysis by X-ray or electron radiation An infrared (IR) emission spectroscopy and microscopy apparatus with X-ray excitation or electron excitation and an improved process for extending spatial relation of infrared (IR) microscopy and performing microscopic infrared (IR) analysis by X-ray or electron rad... | 01/31/2012 |
| 8103930 | Apparatus for implementing processor bus speculative data completion A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrect... | 01/24/2012 |
| 8103900 | Implementing enhanced memory reliability using memory scrub operations A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent per... | 01/24/2012 |
| 8098729 | Implementing B-picture scene changes A method and apparatus are provided for implementing B-picture scene changes. A prediction stage predicts a B-picture scene change based upon a sequence of statistical information in an encoder order and a reaction stage is responsive to the prediction stage for mod... | 01/17/2012 |
| 8089285 | Implementing tamper resistant integrated circuit chips A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the se... | 01/03/2012 |
| 8089199 | Mechanical design of laminar weak-link rotary mechanisms with ten-degree-level travel range and ten-nanoradian-level positioning resolution Enhanced mechanical designs are provided for weak-link rotary mechanisms for implementing angular rotations with a defined angular travel range and positioning resolution, for example, with ten-degree-level travel range and ten-nanoradian-level positioning resolutio... | 01/03/2012 |
| 8086924 | Implementing diagnosis of transitional scan chain defects using logic built in self test LBIST test patterns A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple syste... | 12/27/2011 |
| 8085550 | Implementing enhanced solder joint robustness for SMT pad structure A method and a surface mount technology (SMT) pad structure are provided for implementing enhanced solder joint robustness. The SMT pad structure includes a base SMT pad. The base SMT pad receives a connector for soldering to the SMT pad structure. A standoff struct... | 12/27/2011 |
| 8083067 | Method for the separation of overlapping density porous materials from less porous materials Enhanced methods for separating of overlapping density porous materials are provided. The methods of the invention exploit the differences in the porosity of porous feed materials compared to that of the solid plastics. In the first stage, air is forced out of the p... | 12/27/2011 |
| 8065575 | Implementing isolation of VLSI scan chain using ABIST test patterns A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array... | 11/22/2011 |
| 8056018 | Implementing registration and conflict resolution of web application keyboard shortcuts Conflict resolution of web application keyboard shortcuts implementation includes a web application being loaded in a web browser and application keyboard shortcuts for the web application are registered with the web browser. The web browser identifies application k... | 11/08/2011 |
| 8055733 | Method, apparatus, and computer program product for implementing importation and converging system definitions during planning phase for logical partition (LPAR) systems Hardware and partition information of an existing LPAR system is collected and stored in a first system plan file. The first system plan file is applied to a partition planning tool. The partition planning tool identifies hardware to be reused in a second LPAR syste... | 11/08/2011 |
| 8053352 | Method and mesh reference structures for implementing Z-axis cross-talk reduction through copper sputtering onto mesh reference planes A method and mesh reference applications are provided for implementing Z-axis cross-talk reduction. A mesh reference plane including a grid of mesh traces is formed with the mesh traces having selected thickness and width dimensions effective for reference current-f... | 11/08/2011 |
| 8049526 | Enhanced speed sorting of microprocessors at wafer test A method and apparatus are provided for implementing optimized speed sorting of microprocessors at wafer test. A combination of speed-predicting metrics are measured early in the manufacturing process and are applied to a unique algorithm to properly sort parts into... | 11/01/2011 |
| 8037059 | Implementing aggregation combination using aggregate depth lists and cube aggregation conversion to rollup aggregation for optimizing query processing A process combines multiple grouping sets into single rollup sets with depth lists defining the levels of grouping that must be performed. Grouping sets are identified that are contained within other sets and combined into single rollups with depth lists. Cube aggre... | 10/11/2011 |
| 8015565 | Preventing livelocks in processor selection of load requests A method, and apparatus are provided for preventing livelocks in processor selection of load requests in a multiprocessor (MP) system. On random occasions a selection mechanism is changed for first holding up all requests and then a random selection is made. Then a ... | 09/06/2011 |
| 8015191 | Implementing dynamic processor allocation based upon data density Dynamic processor allocation is implemented based upon bitmap data density. A bitmap index is used to process the query. A bitmap is created for the query. The bitmap is partitioned into single I/O operations. A variable partition size is provided based upon data de... | 09/06/2011 |
| 8013744 | Radio frequency identification (RFID) surveillance tag An enhanced method and apparatus are provided for tracking and managing a plurality of packagings, particularly packagings containing radioactive and fissile materials. A radio frequency identification (RFID) surveillance tag is provided with an associated packaging... | 09/06/2011 |
| 8007291 | Implementing differential signal circuit board electrical contact A method, and structures are provided for implementing differential signal circuit board electrical contact. A removable member including a pair of independent electrical contacts is removably received within an associated contact-receiving cavity on the circuit boa... | 08/30/2011 |
| 8001354 | Implementing dynamic physical memory reallocation A computer system, computer program product, and method implement dynamic physical memory reallocation. A system management interface (SMI) Handler and an Operating System (OS) are arranged for exchanging communications. Periodically the SMI Handler queries the oper... | 08/16/2011 |
| 7994797 | Implementing a coded time domain transmission distance meter A method and circuit for implementing a coded time domain transmission distance meter, and a design structure on which the subject circuit resides are provided. A first transmitter module connected to a cable at a first point or power outlet, generates and sends a t... | 08/09/2011 |
| 7994688 | Mechanical design of laminar weak-link mechanisms with centimeter-level travel range and sub-nanometer positioning resolution An enhanced mechanical design for laminar weak-link mechanisms with centimeter-level travel range and sub-nanometer positioning resolution is provided. A multiple parallelogram weak-link structure includes a predefined pattern of a plurality of perpendicularly arran... | 08/09/2011 |
| 7989918 | Implementing tamper evident and resistant detection through modulation of capacitance A method and tamper detection circuit for implementing tamper and anti-reverse engineering evident detection in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A capacitor is formed with the semiconductor chip includin... | 08/02/2011 |
| 7989337 | Implementing vertical airgap structures between chip metal layers A method and structure are provided for implementing vertical airgap structures between chip metal layers. A first metal layer is formed. A first layer of silicon dioxide dielectric is deposited onto the first metal layer. A vertical air gap is etched from the first... | 08/02/2011 |
| 7985095 | Implementing enhanced connector guide block structures for robust SMT assembly A method and enhanced connector guide block structures implement robust connector assembly including robust Surface Mount Technology (SMT) connector assembly. A connector guide block includes a printed wiring board (PWB) mating face including at least one mounting s... | 07/26/2011 |
| 7984357 | Implementing minimized latency and maximized reliability when data traverses multiple buses A memory controller and methods implement minimized latency and maximized reliability when data traverses multiple buses. The memory controller includes a dynamic random access memory (DRAM) error correcting code (ECC) checking and correcting circuit and a high spee... | 07/19/2011 |
| 7961732 | Method and hardware apparatus for implementing frame alteration commands A method and apparatus are provided for implementing frame alteration commands in a communications network processor. A set of frame alteration instruction templates is defined. A frame alteration instruction template is identified based upon the packet type recogni... | 06/14/2011 |
| 7954642 | Process and apparatus for separating solid mixtures An elutriation column is installed in a separation tank. The elutriation column includes a vertical separation column having a first side feed arm and a second side overflow arm spaced above the first side feed arm. Water is forced upwardly through the vertical sepa... | 06/07/2011 |
| 7954081 | Implementing enhanced wiring capability for electronic laminate packages Structures and a computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package ph... | 05/31/2011 |
| 7945883 | Apparatus, and computer program for implementing vertically coupled noise control through a mesh plane in an electronic package design A method, apparatus and computer program product are provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the e... | 05/17/2011 |
| 7941652 | Apparatus and computer program product for implementing atomic data tracing A method, apparatus and computer program product are provided for implementing atomic data tracing in a processor system including an auxiliary processor unit (APU) coupled to a central processor unit (CPU). The auxiliary processor unit (APU) processes a trace instr... | 05/10/2011 |
| D636517 | Post top lighting fixture | 04/19/2011 |
