Did You Know...
...that the x-ray was discovered purely by accident? When German physicist Wilhelm Konrad von Roentgen was experimenting with cathode rays in 1895, he put an activated Crookes tube in a book and went out to lunch. When he returned, he discovered that a key that had also been placed in the book showed up as an image on the developed film!
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| Number | Title | Issue Date |
| 7749792 | Self-assembling MEMS devices having thermal actuation The present disclosure is broadly directed to a method for designing new MEMS micro-movers, particularly suited for, but not limited to, CMOS fabrication techniques, that are capable of large lateral displacement for tuning capacitors, fabricating capacitors, self-a... | 07/06/2010 |
| 7729542 | Using edges and corners for character input A new unistroke text entry method for handheld or wearable devices is designed to provide high accuracy and stability of motion. The user makes characters by traversing the edges and diagonals of a geometric pattern, e.g. a square, imposed over the usual text input ... | 06/01/2010 |
| 7711964 | Method of securing programmable logic configuration data The present invention relates to a secure method of distributing configuration data for a programmable logic device (PLD). The configuration data is encrypted to generate encrypted configuration data. A decryption key is encrypted using a silicon key. The encrypted ... | 05/04/2010 |
| 7698121 | Device and method for programmable wideband network emulation An emulator for emulating a wireless network comprised of a plurality of RF nodes is comprised of a programmable controller for emulating the movements of the plurality of RF nodes within an emulated space. The controller provides both information and control signal... | 04/13/2010 |
| 7697357 | Negative voltage driving for the digit line isolation gates A system and method to reduce standby leakage current in the event of row-to-column shorts in a memory chip or in an electronic device having memory or data storage elements is disclosed. In case of memory rows or wordlines precharged to a negative wordline voltage ... | 04/13/2010 |
| 7694202 | Providing memory test patterns for DLL calibration A system and method to provide memory test patterns for the calibration of a delay locked loop (DLL) using a pseudo random bit sequence (PRBS) stored in a serial presence detect (SPD) circuit memory. The test bits stored in the SPD memory are transferred to a memory... | 04/06/2010 |
| 7676648 | Method for manipulating data in a group of processing elements to perform a reflection of the data A method for generating a reflection of data in a plurality of processing elements comprises shifting the data along, for example, each row in the array until each processing element in the row has received all the data held by every other processing element in that... | 03/09/2010 |
| D611610 | Medical cart | 03/09/2010 |
| 7669027 | Memory command delay balancing in a daisy-chained memory topology A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIM... | 02/23/2010 |
| 7655508 | Overmolding encapsulation process and encapsulated article made therefrom A method of encapsulating an article having first and second surfaces, includes positioning the article on a carrier such that at least a portion of the first surface contacts the carrier. A portion of the carrier carrying the article is then positioned within a mol... | 02/02/2010 |
| 7629819 | Seamless coarse and fine delay structure for high performance DLL A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate ... | 12/08/2009 |
| 7627793 | Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and generating a second signal having a pseudo-random pattern. The first ... | 12/01/2009 |
| 7626416 | Method and apparatus for high resolution ZQ calibration A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls ... | 12/01/2009 |
| 7624337 | System and method for indexing, searching, identifying, and editing portions of electronic multimedia files A method and system are provided for tagging, indexing, searching, retrieving, manipulating, and editing video images on a wide area network such as the Internet. A first set of methods is provided for enabling users to add bookmarks to multimedia files, such as mov... | 11/24/2009 |
| 7622986 | High performance input receiver circuit for reduced-swing inputs An input buffer receiver circuit for electronic devices (e.g., memory chips) to receive and process reduced-swing and high bandwidth inputs to obtain “buffered” output signals therefrom with symmetrical rising and falling delays, and without additional current d... | 11/24/2009 |
| 7616504 | High speed array pipeline architecture A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output ... | 11/10/2009 |
| 7616242 | Linear-logarithmic pixel sensors and gain control circuits therefor A system and method are disclosed to enlarge the sub-threshold current coefficient “α” of a reset transistor connected to a photodiode in an L-L (Linear Logarithmic) pixel sensor without modifying any semiconductor process parameters. In one embodiment, a coupl... | 11/10/2009 |
| D603048 | Medical cart | 10/27/2009 |
| 7606102 | Memory address repair without enable fuses A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding... | 10/20/2009 |
| 7596678 | Method of shifting data along diagonals in a group of processing elements to transpose the data A transpose of data appearing in a plurality of processing elements comprises shifting the data along diagonals of the plurality of processing elements until the processing elements in the diagonal have received the data held by every other processing element in tha... | 09/29/2009 |
| 7593272 | Detection of row-to-row shorts and other row decode defects in memory devices A system and method to detect row-to-row shorts and other row decode defects in memory devices and other electronic devices having a similar data storage functionality is disclosed. A selective switching between a normal large pull-up device and a smaller one in a w... | 09/22/2009 |
| 7581080 | Method for manipulating data in a group of processing elements according to locally maintained counts The present invention is capable of placing or loading input data into a 2D or 3D array of processing elements interconnected in a variety of ways, and moving the data around by using a combination of shifts, e.g. north, south, east, west, which can be combined in a... | 08/25/2009 |
| 7579862 | MOS linear region impedance curvature correction A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. The linear region... | 08/25/2009 |
| 7574634 | Real time testing using on die termination (ODT) circuit A system and method to operate an electronic device, such as a memory chip, in a test mode using the device's built-in ODT (on die termination) circuit is disclosed. One or more test mode related signals, which include on-die signals and other relevant information, ... | 08/11/2009 |
| 7574466 | Method for finding global extrema of a set of shorts distributed across an array of parallel processing elements A method for finding an extrema for an n-dimensional array having a plurality of processing elements, the method includes determining within each processing element a first dimensional extrema for a first dimension, wherein the first dimensional extrema is related t... | 08/11/2009 |
| 7560956 | Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT porti... | 07/14/2009 |
| 7548565 | Method and apparatus for fast metadata generation, delivery and access for live broadcast program Techniques for fast indexing of live video broadcasts are provided which incorporate both efficient manual processing and automatic indexing steps to generate semantically meaningful and practically usable highlight hierarchy of broadcast television programs in real... | 06/16/2009 |
| 7541648 | Electrostatic discharge (ESD) protection circuit An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs) each with a floating base and a metal oxide semiconductor (MOS) field transistor with a floating body is dis... | 06/02/2009 |
| 7516281 | On-die termination snooping for 2T applications in a memory system implementing non-self-terminating ODT schemes A method and apparatus for controlling the on-die termination of a memory system. The method comprises snooping a command bus in response to a first plurality of command signals clocked at 1T and enabling the on-die termination in response to a second plurality of c... | 04/07/2009 |
| 7512763 | Transparent SDRAM in an embedded environment A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part because it can function without precharge signals, row address latch ... | 03/31/2009 |
| 7503046 | Method of obtaining interleave interval for two data values A method of determining an interleave pattern for n lots of A and y lots of B, when n plus y equals a power of two such that the expression 2z−n may be used to represent the value of y, includes generating a key including the reverse bit order of a seri... | 03/10/2009 |
| 7502511 | Shape grammar interpreter Parametric shape recognition is achieved through a decomposition of shapes into a hierarchy of subshapes ordered by their decreasing restrictions. Instances of each of the subshapes are individually located in the design shape and then reconstructed to form an insta... | 03/10/2009 |
| 7489564 | 256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows i... | 02/10/2009 |
| 7489568 | Delay stage-interweaved analog DLL/PLL A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized de... | 02/10/2009 |
| 7483569 | Reduced complexity correlation filters A methodology is described to reduce the complexity of filters for face recognition by reducing the memory requirement to, for example, 2 bits/pixel in the frequency domain. Reduced-complexity correlations are achieved by having quantized MACE, UMACE, OTSDF, UOTSDF,... | 01/27/2009 |
| 7482855 | Circuit and method for stable fuse detection A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and ... | 01/27/2009 |
| 7480202 | High speed array pipeline architecture A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output ... | 01/20/2009 |
| 7480203 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and ... | 01/20/2009 |
| 7477557 | 256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows i... | 01/13/2009 |
| 7477556 | 256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows i... | 01/13/2009 |
