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| Number | Title | Issue Date |
| 8006033 | Systems, methods, and apparatuses for in-band data mask bit transmission Embodiments of the invention are generally directed to systems, methods, and apparatuses for in-band data mask bit transmission. In some embodiments, one or more data mask bits are integrated into a partial write frame and are transferred to a memory device via the ... | 08/23/2011 |
| 7957216 | Common memory device for variable device width and scalable pre-fetch and page size Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a n... | 06/07/2011 |
| 7954001 | Nibble de-skew method, apparatus, and system De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits. ... | 05/31/2011 |
| 7885914 | Systems, methods and apparatuses for rank coordination Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performan... | 02/08/2011 |
| 7836380 | Destination indication to aid in posted write buffer loading Embodiments of the invention are generally directed to systems, methods, and apparatuses for a destination indication to aid in posted write buffer loading. In some embodiments, a memory device includes a posted write buffer having a first element and a second eleme... | 11/16/2010 |
| 7826522 | Automatic calibration circuit for a continuous-time equalizer Embodiments of the invention are generally directed to systems, methods, and apparatuses for an automatic calibration circuit for a continuous-time equalizer (CTE). In some embodiments, the calibration circuit separately locks the direct (DC) voltage swing and the a... | 11/02/2010 |
| 7787352 | Method for processing a MEMS/CMOS cantilever based memory storage device A Seek and Scan Probe (SSP) memory device is disclosed. The memory device includes a moving part having microelectromechanical (MEMS) structures fabricated on a first wafer and CMOS and memory medium components fabricating on a second wafer bonded to the first wafer... | 08/31/2010 |
| 7668698 | Duty cycle calibration for receiver clock Embodiments of the invention are generally directed to systems, methods, and apparatuses for the direct duty cycle calibration of a receiver clock. In some embodiments, an integrated circuit includes a receive (RX) data path, a RX clock path, and a control path. In ... | 02/23/2010 |
| 7501586 | Apparatus and method for improving printed circuit board signal layer transitions A method and apparatus for improving printed circuit board signal layer transitions are described. In one embodiment, the method includes the formation of a first via within a printed circuit board (PCB). A second via is formed concurrently within the PCB. In one em... | 03/10/2009 |
| 7483390 | System and method for dynamically configuring and transitioning wired and wireless networks A network may be abstracted into four layers: a control layer, a network management layer, a verification and validation layer, and a physical network layer. The control layer interacts with the other three layers to execute network scenarios. The network management... | 01/27/2009 |
| 7464241 | Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding Methods and apparatus for use with memory systems and memory modules are included among the embodiments. In exemplary systems, error-correction coding (ECC) data is temporally multiplexed with user data on the same data bus lines in a burst mode transfer, such that ... | 12/09/2008 |
| 7414426 | Time multiplexed dynamic on-die termination Embodiments of the invention are generally directed to systems, methods, and apparatuses for time-multiplexed dynamic on-die termination. In an embodiment, an integrated circuit receives, during a first clock, an on-die termination (ODT) activation signal at its ODT... | 08/19/2008 |
| 7386629 | System and method for synchronous configuration of DHCP server and router interfaces A system and method for synchronous configuration of DHCP server and router interfaces is disclosed. A network management layer identifies a DHCP server interface and a router interface associated with the same subnet. The network management layer then determines co... | 06/10/2008 |
| 7383340 | System and method for programmatically changing the network location of a network component A system and method for programmatically changing the network location of a network component is disclosed. A network management layer programmatically interrupts a link between the network component and the network. The network management layer then changes the net... | 06/03/2008 |
| 7372293 | Polarity driven dynamic on-die termination Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pi... | 05/13/2008 |
| 7353349 | Method and apparatus for reordering memory requests for page coherency A method and apparatus for reordering memory requests for page coherency. Various data streams are frequently found in separate areas of physical memory (i.e. each data stream is found in a separate memory “page”). Because these requests from different streams b... | 04/01/2008 |
| 7350030 | High performance chipset prefetcher for interleaved channels The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a cha... | 03/25/2008 |
| 7350016 | High speed DRAM cache architecture A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memor... | 03/25/2008 |
| 7346728 | Method and apparatus for a hub capable of being self-powered for use in a USB-compliant system Method and apparatus are described for improving information transfer over USB. In one approach, hub-based extension is realized wherein power is distributed using auxiliary wiring distinct from signal and power wiring present in conventional USB cabling. Additional... | 03/18/2008 |
| 7346716 | Tracking progress of data streamer Machine-readable media, methods, and apparatus are described to stream data between a codec and a buffer in system memory and to maintain a value in system memory that is indicative of a current position in the buffer. In some embodiments, an audio controller stream... | 03/18/2008 |
| 7346795 | Delaying lanes in order to align all lanes crossing between two clock domains In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal t... | 03/18/2008 |
| 7342969 | Signaling with multiple clocks At least two sequences of predetermined reference times are established on respective ones of at least two communication lines. At least some of the reference times of at least one of the sequences occur out-of-phase with at least some of the reference times of anot... | 03/11/2008 |
| 7342411 | Dynamic on-die termination launch latency reduction Embodiments of the invention are generally directed to systems, methods, and apparatuses for dynamic on-die termination launch latency reduction. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and a termination... | 03/11/2008 |
| 7340582 | Fault processing for direct memory access address translation An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested... | 03/04/2008 |
| 7334107 | Caching support for direct memory access address translation An embodiment of the present invention is a technique to provide cache support for direct memory access address translation. A cache structure stores cached entries used in address translation of a guest physical address to a host physical address. The guest physica... | 02/19/2008 |
| 7327370 | Memory controller hub interface A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub... | 02/05/2008 |
| 7328375 | Pass through debug port on a high speed asynchronous link An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge dev... | 02/05/2008 |
| 7279703 | Self-heating burn-in A method and an apparatus for self-heating burn-in have been disclosed. In one embodiment, a semiconductor device includes a plurality of gates, a multiplexer to select a clock signal out of a plurality of clock signals to toggle the plurality of gates in response t... | 10/09/2007 |
| 7279698 | System and method for an optical modulator having a quantum well The optical modulator may include a strained layer of SiGe to confine carriers in a quantum well. The strained layer of SiGe may be doped with arsenic to provide electrons. The optical modulator may receive an optical signal and modulate the received signal by alter... | 10/09/2007 |
| 7277992 | Cache eviction technique for reducing cache eviction traffic A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated b... | 10/02/2007 |
| 7260691 | Apparatus and method for initialization of a double-sided DIMM having at least one pair of mirrored pins A method and apparatus for initialization of a double-sided memory module having a least one pair of mirrored pins. In one embodiment, the method includes the generation of an opcode to initialize a first side of the memory module according to a first side pin routi... | 08/21/2007 |
| 7249232 | Buffering and interleaving data transfer between a chipset and memory modules Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffer... | 07/24/2007 |
| 7245682 | Determining an optimal sampling clock In some embodiments, a phase detector receives a set of sampling clock signals and a data signal and compares each of the clock signals to the data signal. A clock selector selects an optimal sampling clock signal from the set of sampling clock signals based on a tr... | 07/17/2007 |
| 7243205 | Buffered memory module with implicit to explicit memory command expansion Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a ... | 07/10/2007 |
| 7243178 | Enable/disable claiming of a DMA request interrupt Machine-readable media, methods, and apparatus are described for performing direct memory access (DMA) transfers. In some embodiments, a device may generate an interrupt to request a DMA transfer. A DMA controller may claim the interrupt and may prevent a processor ... | 07/10/2007 |
| 7234051 | Method and apparatus for booting from a selection of multiple boot images A method and apparatus for booting from a selection of multiple boot images. Control logic is coupled with a plurality of memory devices containing a plurality of boot images. The control logic employs a device select value to map device requests to memory devices. ... | 06/19/2007 |
| 7228362 | Out-of-order servicing of read requests with minimal additional storage Various embodiments of the invention relate to an apparatus and method for efficiently implementing out-of-order servicing of read requests originating from an input/output (I/O) interface with minimal additional storage. For example, a number of read entries may be... | 06/05/2007 |
| 7225247 | Serial port redirection using a management controller A method and apparatus is provided for serial port redirection using a management controller. A serial controller is selectively coupled with a management controller to facilitate the redirection of serial information. The management controller includes a packetizer... | 05/29/2007 |
| 7188208 | Side-by-side inverted memory address and command buses Generating a pair of buses, each coupled to a common terminating device, each having a set of address signal lines that are coupled to a separate memory device, and driving one set of address signal lines with an address driven with true logic states while driving t... | 03/06/2007 |
| 7180861 | Strict priority distributed coordination function in wireless networks A system and method for prioritizing the transmission of packets in a wireless local area network. A station selects a packet from local priority queuing and identifies the priority bits of the packet. The station declares the priority of the selected packet based o... | 02/20/2007 |
