Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
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| Number | Title | Issue Date |
| 8107575 | Method and circuit for changing modes without dedicated control pin A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency i... | 01/31/2012 |
| 7834378 | SCR controlled by the power bias A composite dual SCR circuit that acts to protect the Vcc node as well as an I/O node or pin. The dual SCR uses the Vcc to control or program the triggering point of the SCR connected to an I/O node. When Vcc is low, the SCR protecting an I/O node triggers a few vol... | 11/16/2010 |
| 7800435 | Audio filter using a diode connected MOSFET A diode connected P-type CMOS transistor is operated in the sub-threshold area and, with a bypass capacitor, operates as a low pass audio filter. The equivalent resistance of the CMOS transistor in the sub-threshold range is very high—in the gigaOhm range. With th... | 09/21/2010 |
| 7782117 | Constant switch Vgs circuit for minimizing rflatness and improving audio performance A MOSFET switch is disclosed that is driven on by a circuit that provides a constant gate to source voltage, Vgs, that is independent of the input voltage, the power supply and any logic signals. The constant Vgs is derived from a reference voltage and biases the MO... | 08/24/2010 |
| 7782116 | Power supply insensitive voltage level translator A circuit is described that when the power supply to circuits that control a pass transistor is at zero volts, the pass transistor configured as a voltage level translator remains off regardless of the voltages and changes in voltages at the ports connected to the p... | 08/24/2010 |
| 7773356 | Stacked SCR with high holding voltage Stacked SCR's are disclosed with a resistor connecting an internal portion of the upper SCR to an internal portion of the lower SCR. The anode of the protective circuit is connected to a contact on a target circuit to be protected and the cathode of the protective c... | 08/10/2010 |
| 7760479 | Technique for combining in-rush current limiting and short circuit current limiting A circuit that protects from high power-on in-rush currents and short circuits. The circuit has a pass transistor and a parallel smaller transistor. A comparator senses when an output voltage crosses a reference and turns off the pass transistor and turns on the par... | 07/20/2010 |
| 7760115 | Low power serdes architecture using serial I/O burst gating A serializer/deserializer is disclosed with a flexible design that allows for sending data streams between computer systems where the power dissipation is markedly reduced by placing the serializer/deserializer in a standby, low power mode between the sending of dat... | 07/20/2010 |
| 7756659 | Delay stabilization for skew tolerance In an integrated circuit with at least two separate timing circuits, for example both a serializer and a deserializer, a trim value correction factor is developed and applied at the testing of the chip. The correction trim value brings the VCO frequency of the seria... | 07/13/2010 |
| 7733248 | Measuring and regenerating a variable pulse width A system and process for receiving a variable pulse width signal and measuring and serially sending the measurements to a receiver that deserializes and regenerates the variable pulse width signal. Data bits may be embedded with the variable pulse width clock measur... | 06/08/2010 |
| 7719026 | Un-assisted, low-trigger and high-holding voltage SCR A protective SCR integrated circuit device is disclosed built on adjacent N and P wells and defining an anode and a cathode. In addition to the anode and cathode contact structures, the device has an n-type stack (N+/ESD) structure bridging the N-Well and the P-Well... | 05/18/2010 |
| 7683693 | Hot swap controller with zero loaded charge pump The present invention includes a pass transistor that limits current drawn from a circuit without using a series resistor and while drawing minimal current from an external supply. A current mirror of the output current is formed and compared to a reference current.... | 03/23/2010 |
| 7554407 | Multi-mode power amplifier with low gain variation over temperature A multi-mode RF amplifier is described having at least a higher and a lower power path coupling an input to an output. At a pre-selected output power level, the higher power path is enabled while the lower power path is disabled when more output power is required. T... | 06/30/2009 |
| 7554382 | Method for reducing insertion loss and providing power down protection for MOSFET switches An FET switch comprising a single or parallel opposite polarity FETS is illustrated with wells that are driven from internal power rails. The internal power rails are logically coupled by other driving FET switches to, in one case, the higher of a positive power sup... | 06/30/2009 |
| 7538614 | Differential amplifier with independent output common mode adjustment A fully differential amplifier with a high common mode rejection ratio with an independent output voltage setting is disclosed. The amplifier may be arranged with a single ended output or a differential output. The gain may be set by adjusting a resistor without aff... | 05/26/2009 |
| 7535309 | Low power, temperature and frequency, tunable, on-chip clock generator A tunable, low power clock generator employs a voltage regulator, one or current generators and a variable resistor bank that, together, produce a control voltage for trimming a VCO. The control voltage is arranged to also compensate, at least, for the variables of ... | 05/19/2009 |
| 7518446 | Multi-mode power amplifier with reduced low power current consumption A multi-mode RF amplifier is disclosed having high and low output power modes composed of two power paths. When the multi-mode RF amplifier is biased into the high power, HP, mode, substantial power is delivered via both (first and second) paths. While in the low po... | 04/14/2009 |
| 7514983 | Over-voltage tolerant pass-gate A pass-gate having a single or parallel opposite polarity FETs is disclosed. The wells of the primary transistor switches are driven from circuitry that reduces over-voltage leakage and other malfunctions. A circuit that drives the wells is also used to power enable... | 04/07/2009 |
| 7479827 | Multi-mode power amplifier with high efficiency under backoff operation A multi-mode RF amplifier is disclosed having high and low output power modes and two power paths. A first RF amplifier delivers power to both paths. When the multi-mode RF amplifier is biased into the high power, HP, mode, substantial power is delivered via both (f... | 01/20/2009 |
| 7468685 | Clockless serialization using delay circuits A serializer is described that incorporates a register and a delay circuit for each serial bit. The serializer provides a timing signal that is generated and output simultaneously with the output of the data bit that ensures close timing alignment of the data bit an... | 12/23/2008 |
| 7427897 | Power amplifier with close-loop adaptive voltage supply A two-(or multi)stage power amplifier receives a variable RF input signal, and outputs an optimized. RF output signal from, for example, a mobile handset. The output power level from the handset is predetermined, as known in the art, by the received control signal f... | 09/23/2008 |
| 7414461 | Linearization technique for current mode filters A circuit is disclosed that compensates for the non-linearity of a current mode real pole producing circuit used to generate poles and zeros in complex filter circuits. The non-linearity of the prior art is compensated by driving one end of the primary pole producin... | 08/19/2008 |
| 7411455 | High output current buffer A bipolar high output current buffer is disclosed using a negative feedback current mirror to supply the base drive to an output transistor. Small quiescent currents are used wherein the buffer demonstrates low quiescent power dissipation. The current mirror supplie... | 08/12/2008 |
| 7411431 | Dual output differential line driver using single current Box switches are stacked sharing a common current from power sources. The power sources may be current, voltage or a combination of such sources. In preferred embodiments, the transistor switches in the box switches may be paralleled by different polarity transistor... | 08/12/2008 |
| 7286358 | Surface mounted resistor with improved thermal resistance characteristics A surface mountable resistor chip assembly, containing an integral heat sink, convective cooling provision exhibits higher continuous-mode power ratings than prior art surface mount resistors having comparable printed circuit board footprints. The preferred embodime... | 10/23/2007 |
| 7248122 | Method and apparatus for generating a serial clock without a PLL A clock circuit for outputting serial data without using a PLL is described. The clock is a VCO designed to start at a frequency that is slightly higher than necessary to preserve the data. The frequency of the clock is measured and if the frequency is too high or t... | 07/24/2007 |
| 7245083 | Incandescent lamp with integral controlling means An incandescent lamp has incorporated a circuit board within a recess in the bulb, wherein the circuit board contains connections and circuitry to control power to the lamp filament while maintaining the attachment of the bulb to the metal base, wherein the complete... | 07/17/2007 |
| 7154307 | Current transfer logic A current mode transfer logic system suitable for driving transmission lines is disclosed. In one embodiment a twisted pair transmission line is terminated in its characteristic line impedance. A signal is formed of two unequal currents, preferably of different pola... | 12/26/2006 |
| 7145378 | Configurable switch with selectable level shifting A configurable bus switch is described where the bus switches are grouped into combinations as determined by logic inputs. NMOS transistors are the bus switches of choice, and programmable logic inputs select and enable groupings of these switches. Switch enable sig... | 12/05/2006 |
| 7141325 | Integrated fuel cell power conditioning with added functional control A power system with a fuel cell array is integrated with power, conversion and control circuitry forming an assembly on a single chip. The power system may include mounted discrete components or flip chips. The power transistors may be built with contacts on both to... | 11/28/2006 |
| 7098610 | Incandescent light power controller with predetermined off-state impedance An incandescent light bulb life extender circuit is designed to attach to the screw base of a conventional light bulb or incorporated in series with the AC powering the bulb. The circuit employs a bidirectional semiconductor switch that reduces the brightness of the... | 08/29/2006 |
| 7095266 | Circuit and method for lowering insertion loss and increasing bandwidth in MOSFET switches A DC symmetrical FET switch includes second and third switches connecting the well of the symmetrical FET switch to the drains and the source when the symmetrical FET switch is on. When the three FET's are on, the well, source and drain of the symmetric FET switch a... | 08/22/2006 |
| 7078305 | High value split poly P-resistor with low standard deviation A resistor structure is disclosed that is constructed out of two layers of polysilicon. The intrinsic device is made using the top layer which is either a dedicated deposition, or formed as part of an existing process step such as a base epi growth in a BiCMOS flow.... | 07/18/2006 |
| 7079369 | Active power/ground ESD trigger An ESD protective triggering circuit for a triggering circuit for a solid state ESD protective device. The arrangement is to provide a controlled current to the protective device that triggers the device so that the device snaps-back and additionally the triggering ... | 07/18/2006 |
| 7064690 | Sending and/or receiving serial data with bit timing and parallel data conversion A serializer and a deserializer are disclosed and shown operating singly or as a pair. The invention operates independently from any outside system reference clock. The inventive system provides an internal bit clock that serializes the data when sending and de-seri... | 06/20/2006 |
| 7030669 | Circuit to linearize gain of a voltage controlled oscillator over wide frequency range A voltage controlled oscillator circuit is shown using multiple delay stages with the last stage looped back out of phase to the first stage. Each stage delay is formed by charging one or more capacitors. The circuitry uses active components demonstrating a square l... | 04/18/2006 |
| 7018778 | Single polisilicon emitter bipolar junction transistor processing technique using cumulative photo resist application and patterning A process for forming a bipolar transistor where the doping implantation of the extrinsic base regions does not affect the emitter doping levels. The techniques is to not remove the photoresist layer used to define the poly emitter contact. The photoresist layer for... | 03/28/2006 |
| 6992624 | Attitude determination system using null-steered array Apparatus and process for determining the position and heading or attitude of an antenna array are described based on radiating sources, preferably GNSS or other such satellite positioning systems. An optimum satellite is selected and the antenna array is “null st... | 01/31/2006 |
| 6980031 | Crosspoint switch with serializer and deserializer functions A programmable switch of three or more ports, each port having data lines separate from lines sharing control and addressing. The programmable switch includes internal logic control and electronic modules that accept and deserialize the control and address signals. ... | 12/27/2005 |
| 6972472 | Quasi self-aligned single polysilicon bipolar active device with intentional emitter window undercut An emitter stack for a quasi-self-aligned bipolar (NPN or PNP) transistor is formed where two layers over the emitter of a silicon substrate are windowed in a manner to under cut the top layer thereby exposing the substrate material. The emitter polysilicon structur... | 12/06/2005 |
