Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Number | Title | Issue Date |
| 7242057 | Vertical transistor structures having vertical-surrounding-gates with self-aligned features The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silico... | 07/10/2007 |
| 7170174 | Contact structure and contact liner process A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a sacrificial contact medium having an opening therein that is lined with a cond... | 01/30/2007 |
| 7109113 | Solid source precursor delivery system A solid source precursor material is delivered to a deposition chamber in vaporized form by utilizing a solid source precursor delivery system having either single or multiple stations(s) having a collection/delivery reservoir that is an intermediate stage between a... | 09/19/2006 |
| 7101747 | Dual work function metal gates and methods of forming Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconducto... | 09/05/2006 |
| 7091087 | Optimized flash memory cell A flash memory comprising floating gate devices being connected to one-another through their source electrodes being self-aligned to their respective gate electrodes, a local tungsten interconnect making a substantially continuous connection to the sources. The flas... | 08/15/2006 |
| 7049206 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 05/23/2006 |
| 7012024 | Methods of forming a transistor with an integrated metal silicide gate electrode Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the metal with epitaxial silicon while residing in a trench to form metal si... | 03/14/2006 |
| 6982894 | Three-dimensional magnetic memory array with a minimal number of access conductors therein and methods thereof A structure and method for forming a magnetic memory having a number N of levels of magnetic memory cells by forming a plurality of levels of magnetic memory cells, each level including at least one magnetic memory core structure having first and second surfaces, fo... | 01/03/2006 |
| 6974774 | Methods of forming a contact opening in a semiconductor assembly using a disposable hard mask Methods to form contact openings and allow the formation of self-aligned contacts for use in the manufacture of semiconductor devices are described. During formation of a multi-layered resist, a hard mask material is introduced beneath an anti-reflective coating to ... | 12/13/2005 |
| 6924969 | Silicon nanocrystal capacitor and process for forming same A storage capacitor plate for a semiconductor assembly having a substantially continuous porous conductive storage plate comprising silicon nanocrystals residing along a surface of a conductive material and along a surface of a coplanar insulative material adjacent ... | 08/02/2005 |
| 6448133 | Method to form a DRAM capacitor using low temperature reoxidation An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitrid... | 09/10/2002 |
| 5591680 | Formation methods of opaque or translucent films The present invention develops an opaque or translucent glass film for use in semiconductor fabrication processes, such as in EPROMs or radio frequency integrated circuits. The opaque or translucent film is developed by forming an glass layer while and in... | 01/07/1997 |
| 5504831 | System for compensating against wafer edge heat loss in rapid thermal processing A method for compensating against wafer edge heat loss during rapid thermal processing includes a semiconductor wafer that is exposed to uniform radiant energy across the entire wafer surface. The wafer is exposed by projecting a radiant energy image onto... | 04/02/1996 |
| 5492597 | Method of etching WSix films The present invention teaches a method for etching a tungsten silicide (WSix) film overlying a polysilicon film in an enclosed chamber during a semiconductor fabrication process, by the steps of: providing a patterned mask overlying the WSi | 02/20/1996 |
| 5474955 | Method for optimizing thermal budgets in fabricating semconductors The present invention teaches a method for fabricating semiconductors. The method initially comprises the step of forming a conformal layer superjacent at least two conductive layers. The conformal layer preferably comprises tetraethylorthosilicate ("TEOS... | 12/12/1995 |
| 5453396 | Sub-micron diffusion area isolation with SI-SEG for a DRAM array The present invention is a process for forming diffusion areas and field isolation regions on a silicon substrate, by the steps of: growing a field oxide layer on the surface of the substrate; forming a mask pattern which exposes a plurality of spaced-apa... | 09/26/1995 |
| 5444408 | Active pull-up voltage spike reducer An embodiment of the present invention provides a method to reduce a regulated power source voltage spike during operation of a dynamic random access memory by the steps of: providing a voltage spike reducer enabling pulse via a pulse generator circuit re... | 08/22/1995 |
| 5425392 | Method DRAM polycide rowline formation The present invention teaches a method for reducing sheet resistance in the fabrication of semiconductor wafers. A silicon substrate having a gate oxide layer thereon is provided in a chamber. Subsequently, a polysilicon layer is formed superjacent the ga... | 06/20/1995 |
| 5418180 | Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon An embodiment of the present invention depicts a storage capacitor comprising: a bottom plate structure having a hemispherical grain silicon surface; a titanium nitride layer adjacent and coextensive the hemispherical grain silicon; an insulating layer ad... | 05/23/1995 |
| 5407534 | Method to prepare hemi-spherical grain (HSG) silicon using a fluorine based gas mixture and high vacuum anneal The present invention develops a process for forming hemi-spherical grained silicon storage capacitor plates by the steps of: forming a silicon layer over a pair of neighboring parallel conductive lines, the silicon layer making contact to an underlying c... | 04/18/1995 |
| 5406263 | Anti-theft method for detecting the unauthorized opening of containers and baggage A simple trip-wire or magnetic circuit associated with a shipping container monitors continuity, which is detected electrically. Simply, if continuity is disabled by a forced entry of the container, electrical detection means, such as a radio-frequency-id... | 04/11/1995 |
| 5384284 | Method to form a low resistant bond pad interconnect The present invention develops a bond pad interconnect in an integrated circuit device, by forming an aluminum pad; bonding a metal layer (such as copper (Cu), nickel (Ni), tungsten (W), gold (Au), silver (Ag) or platinum (Pt)) or a metal alloy (such as t... | 01/24/1995 |
| 5376577 | Method of forming a low resistive current path between a buried contact and a diffusion region The present invention is a Static Random Access Memory fabrication process for forming a buried contact, by the steps of: patterning a photoresist layer over the field silicon dioxide regions and the spaced apart areas of the substrate, thereby providing ... | 12/27/1994 |
| 5371701 | Stacked delta cell capacitor A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent stora... | 12/06/1994 |
| 5364814 | Germanium implanted stacked capacitor cell A method of fabricating a stacked capacitor memory cell having a reduced leakage storage node includes the steps of providing a P-type substrate, forming wordlines on a thin gate oxide layer and a field oxide layer, and forming a first conformal TEOS oxid... | 11/15/1994 |
| 5362632 | Barrier process for Ta2 O5 capacitor The method of the present invention introduces a fabrication method for forming a storage capacitor on a supporting silicon substrate of a semiconductor device, by the steps of: forming a bottom capacitor electrode comprising conductively doped polysilico... | 11/08/1994 |
| 5361002 | Voltage compensating CMOS input buffer The CMOS voltage compensating input buffer circuit of the present invention provides a means to stabilize input level trip points and is comprised of a voltage compensating circuit having an input node and an output drive node coupled to an input buffer. ... | 11/01/1994 |
| 5361003 | Adjustable buffer driver The basic concept of the present invention comprises converting a standard buffer circuit into an adjustable buffer circuit that will in effect reduce the operating speed and power consumption of the IC in which it is constructed. An adjustable buffer cir... | 11/01/1994 |
| 5354705 | Technique to fabricate a container structure with rough inner and outer surfaces The present invention provides a method for forming conductive container structures on a supporting substrate of a semiconductor device, by: forming an insulating layer over parallel conductive lines and existing material on the surface of the supporting ... | 10/11/1994 |
| 5346587 | Planarization of a gate electrode for improved gate patterning over non-planar active area isolation The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height ... | 09/13/1994 |
| 5346836 | Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects A process for forming low resistance contacts between silicide areas and upper level polysilicon interconnect layers including a specific doping technique that provides solid low resistance contacts between a lower level of a silicided area and an upper l... | 09/13/1994 |
| 5340765 | Method for forming enhanced capacitance stacked capacitor structures using hemi-spherical grain polysilicon The present invention develops a container capacitor by forming a conductively doped polysilicon plug between a pair of neighboring parallel conductive word lines; forming a planarized tetra-ethyl-ortho-silicate (TEOS) insulating layer over the parallel c... | 08/23/1994 |
| 5340763 | Multi-pin stacked capacitor utilizing micro villus patterning in a container cell and method to fabricate same The present invention provides production repeatable process to form polysilicon storage node structures using MVP technology. The storage node is formed over word lines beginning with a deposition and planarization of an insulator or composite insulator.... | 08/23/1994 |
| 5336908 | Input EDS protection circuit The input ESD protection circuit of the present invention uses a series n+ active area resistor placed in an n-well placed in series with shunt transistor all of which are in parallel with an SCR shunt to ground circuit, thereby providing greater than +/-... | 08/09/1994 |
| 5334862 | Thin film transistor (TFT) loads formed in recessed plugs The invention is directed to a thin film transistor (TFT) fabricated by using a recessed planarized poly plug as the bottom gate and a recessed planarized poly plug for the TFT drain connecting region. The TFT of the present invention can be used in any i... | 08/02/1994 |
| 5324681 | Method of making a 3-dimensional programmable antifuse for integrated circuits The invention is directed to a concept to use a 3-dimensional DRAM capacitor as a one-time non-volatile programming element (programmable antifuse) to make redundancy repair and/or to select other options on a DRAM. The programmable element of the present... | 06/28/1994 |
| 5323150 | Method for reducing conductive and convective heat loss from the battery in an RFID tag or other battery-powered devices The present invention introduces a method of reducing conductive and convective heat loss from the battery unit in battery-powered devices, such as RFID tag devices. Battery heat loss prevention is accomplished by suspending the battery in a vacuum or wit... | 06/21/1994 |
| 5321649 | Stacked delta cell capacitor A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent stora... | 06/14/1994 |
| 5321648 | Stacked V-cell capacitor using a disposable outer digit line spacer A stacked v-cell (SVC) capacitor using a modified stacked capacitor storage cell fabrication process. The SVC capacitor is made up of polysilicon structure, having a v-shaped cross-section, located at a buried contact and extending to an adjacent storage ... | 06/14/1994 |
| 5304506 | On chip decoupling capacitor The present invention discloses an on chip decoupling capacitor structure having a first decoupling capacitor with one electrode formed in the conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. The second e... | 04/19/1994 |
