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| Number | Title | Issue Date |
| 7483296 | Memory device with unipolar and bipolar selectors A memory device is proposed. The memory device includes a plurality of memory cells, wherein each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The selecto... | 01/27/2009 |
| 7221913 | Effective time-of-arrival estimation algorithm for multipath environment An algorithm identifies a line-of-sight (LOS) signal that may be used to provide an effective time-of-arrival (TOA) estimation. ... | 05/22/2007 |
| 7176842 | Dual band slot antenna A slot antenna having one or more electronic components attached across a slot of the antenna to provide either an RF open or an RF short based on the bias supplied to a control terminal of the electronic component. The antenna is tunable via the RF open or short ac... | 02/13/2007 |
| 7177293 | Terminal assisted scheduling for time coordinated CDMA A telecommunications system supports a variety of packet data services with throughputs ranging from low to high data rates. The system controls the user data transmission over a channel according to the user data throughput requirements of the application. By prope... | 02/13/2007 |
| 7133970 | Least mean square dynamic cache-locking A dynamic cache-locking algorithm may determine the most frequently used function(s) and the number of cache lines that should be locked into the instruction cache embedded into a processor. By evaluating the dynamic cache-locking algorithm, a determination may be m... | 11/07/2006 |
| 7069042 | Quadrature direct synthesis discrete time multi-tone generator A tone generator in a transceiver of a communications device may generate an arbitrary signal using two shift registers to generate the time intervals. During each time interval, a different capacitor is switched onto the node to change the voltage potential on that... | 06/27/2006 |
| 7054218 | Serial memory address decoding scheme A decode circuit for a memory that uses “sequential addressing” includes a series of decoders form a shift register that may be used to provide either wordlines or column select lines for accessing the memory. A pulse generator supplies an appropriate number of ... | 05/30/2006 |
| 7013133 | Portable communication device that may permit one wireless network to communicate with another wireless networks and method therefor Briefly, in accordance with one embodiment of the invention, a portable computing or communication device includes a classmark. A first network may poll the portable communication device and alter the classmark, and thus, alter how a second network interacts with th... | 03/14/2006 |
| 7010706 | Apparatus having a first circuit supplying a power potential to a second circuit under a first operating mode otherwise decoupling the power potential Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator that is used to provide a power supply potential to a memory circuit while a logic circuit is decoupled from a power supply potential. ... | 03/07/2006 |
| 6975846 | Method and circuit to reduce intermodulation distortion Briefly, in accordance with an embodiment of the invention, a method and circuit to reduce intermodulation distortion is provided, wherein the method includes receiving a baseband signal and an interferer signal located in a frequency band and attenuating the interf... | 12/13/2005 |
| 6944713 | Low power set associative cache A processor having an L1 cache memory that may use a compare circuit to determine matches of stored tag information against an address and gate sense amps of the cache memory with a cache-hit signal. ... | 09/13/2005 |
| 6925015 | Stacked memory device having shared bitlines and method of making the same Briefly, in accordance with one embodiment of the invention, a system includes a memory array. The memory array comprises a first layer of memory cells overlying a second layer of memory cells and bit lined coupled to at least one memory cell in the first layer of m... | 08/02/2005 |
| 6914289 | Hourglass ram An integrated circuit having a non-volatile HGRAM cell includes a first section having impurity materials implanted into a substrate to form NPN transistor regions and a second section having a gate structure to control the currents conducted in the NPN transistor r... | 07/05/2005 |
| 6879807 | Remote access unit for wireless wide-area data networking A system is disclosed having a remote access unit and two transceiver modes, one for implementing wireless wide area network communications and another for implementing local wireless network communications. High speed data communications with a cellular system may ... | 04/12/2005 |
| 6862160 | Apparatus providing electronstatic discharge protection having current sink transistors and method therefor An electrostatic discharge circuit may include an RC timer that may be used to control the operation of two or more tiers within the ESD circuit. ... | 03/01/2005 |
| 6801470 | Digital regulation circuit A self-adjusting circuit provides a reverse body bias to circuitry in a DROWSY mode. Memory cells having the appropriate skews are supplied with a changing operating voltage potential, causing a memory cell to fail and determining the correct back bias potential V | 10/05/2004 |
| 6795877 | Configurable serial bus to couple baseband and application processors A system includes an application processor and a baseband processor that may be configurable to communicate by the transfer of data in a hexadecimal format, an octal format or a decimal format in accordance with programmed bits in a register's data field. ... | 09/21/2004 |
| 6791889 | Double data rate memory interface A system supports Double Date Rate (DDR) or Single Data Rate (SDR) data transfers on a data bus between a processor and a memory device. A controller-side interface block connects to a memory-side interface block for generating the control signals and transferring s... | 09/14/2004 |
| 6774696 | Level shifter and voltage translator A level translator block receives a control signal and a data signal and provides an interface between circuitry operating in a first voltage domain and circuitry operating in a second voltage domain. Thick-oxide transistors are appropriately used in the level trans... | 08/10/2004 |
| 6775180 | Low power state retention An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when ... | 08/10/2004 |
| 6707753 | Low power domino tree decoder An integrated circuit having CMOS domino logic arranged in multistages or a tree structure. The multistage cells and addressing structure may have applications in a decoder and reduce the number of cells being precharged and reduce the operating power. ... | 03/16/2004 |
| 6316968 | Sense amplifier circuit A sense amplifier circuit (10) utilizes two current mirror amplifiers (11, 12) to determine the state of the memory cell. Multiple current mirrors are used in order to determine which of four possible states are stored in the memory. A reference circuit (... | 11/13/2001 |
| 6281889 | Moire cancellation circuit A circuit (300) for reducing Moire effects in a display by delaying in alternate horizontal display lines a received horizontal drive pulse (HDRV IN), the circuit having: a current source arrangement (304, 314.1-314.n, 316.1-316.n) for tracking the displa... | 08/28/2001 |
| 6266807 | Method and system for executing instructions in an application-specific microprocessor A method for executing instructions on an application-specific microprocessor having a machine language is described. Microcontroller-like instructions are provided in a virtual language for execution on the processor. High-level DSP-like functions are co... | 07/24/2001 |
| 6259318 | Method for extending the liner range of an amplifier A transceiver (10) includes a transmitter (16) that receives a digital data stream from a digital signal processor (18) to delay lines (20, 30). The delay lines (20,30) provide an address to a ROM look-up table (40). Another input of the look-up table (40... | 07/10/2001 |
| 6249170 | Logarithmic gain control circuit and method An improved logarithmic amplifier (100) and method in which a signal at an output (106) is logarithmic with respect to the voltage supplied at a gain control input (102). The logarithmic amplifier (100) includes a first amplifier stage (110) and a second ... | 06/19/2001 |
| 6242892 | Portable electronic device and method A portable electronic device such as a mobile telephone is powered by a battery and is arranged to operate in an off-mode, a standby mode and an on-mode of operation. Primary electronic circuitry, operable only during the on-mode, provides the main featur... | 06/05/2001 |
| 6211747 | Wideband modulated fractional-N frequency synthesizer A direct modulation multi-accumulator fractional-N frequency synthesizer 1 for generating a carrier signal 150 modulated by a modulation signal 170, 121 is disclosed. The frequency synthesizer includes a Voltage Controlled Oscillator, VCO 50, having a tun... | 04/03/2001 |
| 6187216 | Method for etching a dielectric layer over a semiconductor substrate A wet etch bath (61) holds a wet etchant (52) for etching a dielectric over a semiconductor substrate. The wet etch bath (61) has a tub (63) separated from a reservoir (64) by a wall (65). The tub (63) is filled with the wet etchant (52) to a height of th... | 02/13/2001 |
| 6182104 | Circuit and method of modulo multiplication A co-processor (44) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (56) receives sixteen bit data values stored in an A/B RAM (72) and generates a partial product.... | 01/30/2001 |
| 6177832 | High frequency differential to single-ended converter A differential to single-ended converter which combines a pair of applied differential signals of a given frequency applied into a single-ended signal supplied to an output thereof, including capacitive means (14,16 or 36) coupled across a pair of termina... | 01/23/2001 |
| 6175346 | Display driver and method thereof A display driver circuit having graphics and bilevel modes drives a display (110). A column control circuit (112) includes a shift register (302) with display blanking and bi-directional shifting for scanning the display (110) in either direction for driv... | 01/16/2001 |
| 6175224 | Regulator circuit having a bandgap generator coupled to a voltage sensor, and method A regulator (200) has a pass transistor (250) for transferring a voltage from an input (202) to an output (205). A voltage sensor (231) at the output (205) carries a PTAT current (IA) A generator with diode or transistor chains (271, 272) deriv... | 01/16/2001 |
| 6169800 | Integrated circuit amplifier and method of adaptive offset Alert amplifier (10) has a peak detector (22) and an operational amplifier (30) that dynamically set a bias voltage of a transducer (32) to minimize the standby current. In the absence of an input ring signal at an input terminal (12), the standby current... | 01/02/2001 |
| 6166556 | Method for testing a semiconductor device and semiconductor device tested thereby A test substrate (30) including a plurality of solder bumps (38) is used to test a die (10) which can be used as either a wire-bonded device or a flip-chip device. Die (10) includes test pads (14) which are redundant electrical connections to bond pads (1... | 12/26/2000 |
| 6150881 | Amplifier circuit with amplitude and phase correction and method of operation A correction circuit (10) includes a transistor (30) that generates a feedback signal for equalizing the amplitude and adjusting the phase of the output signals (VOUT- and VOUT+) that are provided at the output of the variable gain a... | 11/21/2000 |
| 6147551 | Switched capacitor circuit and method for reducing sampling noise A switched capacitor circuit (60) reduces sampling noise by oversampling an input signal in space domain. The switched capacitor circuit (60) includes four sampling capacitors (72, 74, 76, 78) serially coupled together via five integrating switches (71, 7... | 11/14/2000 |
| 6144977 | Circuit and method of converting a floating point number to a programmable fixed point number A programmable numeric converter (10) converts a floating point number to a fixed point format by selecting the proper offset. The mantissa is loaded with an implied value one into the least significant, or most significant, bits of the shifter (20). The ... | 11/07/2000 |
| 6144846 | Frequency translation circuit and method of translating A frequency translation circuit (10) translates an incoming reference signal (RFIN) to a lower frequency using a compound mixer circuit (42). The compound mixer circuit (42) has a first mixer circuit (14A) that receives both the incoming refere... | 11/07/2000 |
| 6139079 | Universal transport apparatus A transport head (10) and a method for transporting flux and solder balls (50) to locations for bonding pads (46) on a workpiece (44). To transfer flux, a first pattern definition mask (12) is attached to the transport head (10) and allows selector pins (... | 10/31/2000 |
