Quotables
"Rail travel at high speeds is not possible because passengers, unable to breathe, would die of asphyxia."
Dionysius Lardner, Professor of Natural Philosophy and Astronomy at University College, London ; 1830
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| Number | Title | Issue Date |
| 8123580 | Interface system for segmented surfboard A waterboard includes a head segment having a concave rear edge, a tail segment having a convex front edge, an interface system adapted to removably connect the head and tail segments together. The interface system includes a head interface connecter having a convex... | 02/28/2012 |
| 8111533 | System for dynamically managing power consumption in a search engine The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating th... | 02/07/2012 |
| 8089793 | Dynamic random access memory based content addressable storage element with concurrent read and compare A content addressable memory (CAM) cell includes a first storage element for storing a data value, a second storage element for storing the data value, and a compare circuit having first inputs to receive from the first storage element a first complementary data sig... | 01/03/2012 |
| 8086641 | Integrated search engine devices that utilize SPM-linked bit maps to reduce handle memory duplication and methods of operating same An integrated search engine device evaluates span prefix masks for keys residing at leaf parent levels of a search tree to identify a longest prefix match to an applied search key. This longest prefix match resides at a leaf node of the search tree that is outside a... | 12/27/2011 |
| 8059439 | Encoding data for storage in a content addressable memory An encoding scheme is disclosed that allows a CAM device to selectively store, within each cell of a row of the CAM device, either a single bit of a binary value or two bits of an encoded data word encoded from the binary value. By storing two bits of the encoded da... | 11/15/2011 |
| 8054696 | System and method to improve reliability in memory word line A method and apparatus are disclosed for improving reliability in a memory circuit. The method includes coupling a pull-down element to a word line, the pull-down element coupled distal to a word line driver. The method further includes, when the word line exhibits ... | 11/08/2011 |
| 8051085 | Determining regular expression match lengths A method and apparatus are disclosed for determining the lengths of one or more substrings of an input string that matches a regular expression (regex) The input string is searched for the regex using an non-deterministic finite automaton (NFA), and upon detecting a... | 11/01/2011 |
| 8031503 | System for dynamically managing power consumption in a search engine The power consumption of a search engine such as a CAM device is dynamically adjusted to prevent performance degradation and/or damage resulting from overheating. For some embodiments, the CAM device is continuously sampled to generate sampling signals indicating th... | 10/04/2011 |
| 8031501 | Segmented content addressable memory device having pipelined compare operations Present embodiments describe a CAM device having a segmented CAM array. Each segment of the CAM array, or cell blocks, includes one or more rows of CAM cells. One or more of the cell blocks in the CAM array are selectively enabled during a search operation based on ... | 10/04/2011 |
| 8027930 | Method and apparatus for updating certificate information between buyers and suppliers A computer system that manages compliance information between a buyer and a number of suppliers includes a database and is operable to store supplier guidelines corresponding to a product the buyer desires to purchase, store a list of approved suppliers, provide the... | 09/27/2011 |
| 8023301 | Content addressable memory device having state information processing circuitry Present embodiments allow a search engine to quickly save and restore state information to and from an external state memory when switching between multiple data flows by transferring the state information between the search engine and the external state memory in a... | 09/20/2011 |
| 8023300 | Content addressable memory device capable of parallel state information transfers Present embodiments allow a search engine to quickly save and restore state information to and from an external state memory when switching between multiple data flows by transferring the state information between the search engine and the external state memory in a... | 09/20/2011 |
| 8023299 | Content addressable memory device having spin torque transfer memory cells A CAM device includes an array of CAM cells each having a spin torque transfer (STT) storage cell to store a data bit. Each STT storage cell includes a first magnetic tunnel junction (MTJ) element coupled between a first input node and an output node of the CAM cell... | 09/20/2011 |
| 8023298 | Encoding data for storage in a content addressable memory Approaches for an improved encoding scheme that allows a CAM device to selectively store, within each cell of a row of the CAM device, either a single bit of a binary value or two bits of an encoded data word encoded from the binary value. By storing two bits of the... | 09/20/2011 |
| 7978709 | Packet matching method and system A method of constructing a hierarchical database from an initial plurality of rules. A first rule of the initial plurality of rules is added to: a first sub-database if a first bit of the rule is a logic ‘0’ value; a second sub-database if the first bit is a log... | 07/12/2011 |
| 7953721 | Integrated search engine devices that support database key dumping and methods of operating same Methods of operating a search engine device include repeatedly reading next keys (and associated handles) from a database within the search engine device in order to identify and transfer some or possibly all of the contents of the database to another device (e.g., ... | 05/31/2011 |
| 7944724 | Ternary content addressable memory having reduced leakage effects A column of ternary content addressable memory (TCAM) cells includes a bit line pair that is twisted at a location at or near the center of the column. Data is written to (and read from) TCAM cells located above the twist location with a first bit line polarity. Dat... | 05/17/2011 |
| 7941673 | Copy protection without non-volatile memory An FPGA includes a plurality of configurable logic elements, a configuration circuit, a decryption circuit, and a fingerprint element. The fingerprint element generates a fingerprint that is indicative of inherent manufacturing process variations unique to the FPGA.... | 05/10/2011 |
| 7933885 | Longest matching prefix search engine with hierarchical decoders A search engine searches a database for key candidates having a longest matching prefix with a search key. The search engine includes first stage decoders each having a matrix of interconnected cells for identifying preliminary candidate keys in the database. The se... | 04/26/2011 |
| 7933282 | Packet classification device for storing groups of rules A packet classification device includes a CAM device, an SRAM device, and a control circuit that controls and coordinates the operations of the CAM and SRAM devices. For some embodiments, a first CAM block stores unique entries for each packet header field, a RAM bl... | 04/26/2011 |
| 7924590 | Compiling regular expressions for programmable content addressable memory devices A content search system includes CAM device, a compiler, and an image loader. The CAM device, which includes a plurality of rows of CAM cells and a number of counter circuits selectively interconnected by a programmable interconnect structure (PRS), performs regular... | 04/12/2011 |
| 7924589 | Row redundancy for content addressable memory having programmable interconnect structure A content addressable memory (CAM) device includes an array having a number N of CAM rows, each row including a plurality of CAM cells coupled to a match line, a spare CAM row including a plurality of CAM cells coupled to a spare match line, and row replacement circ... | 04/12/2011 |
| 7920399 | Low power content addressable memory device having selectable cascaded array segments A content addressable memory (CAM) device includes a CAM array and a configuration circuit. The CAM array has a plurality of rows of CAM cells, each row segmented into a plurality of row segments, each row segment including a plurality of CAM cells coupled to a corr... | 04/05/2011 |
| 7920398 | Adaptive match line charging A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and a pre-charge circuit. The detector circuit detects a voltage of the match line and ... | 04/05/2011 |
| 7920397 | Memory device having bit line leakage compensation A memory device operates in a calibration mode during which the effects of bit line leakage current are measured and to operate in a normal mode during which the bit line current is adjusted to compensate for leakage according to the results of the calibration mode.... | 04/05/2011 |
| 7919991 | Comparator circuit A comparator circuit is disclosed that determines whether a first binary value is greater than, equal to, and/or less than a second binary value without employing binary adder circuits, and therefore is simpler, occupies less circuit area, and consumes less power th... | 04/05/2011 |
| 7917486 | Optimizing search trees by increasing failure size parameter A search tree embodying a plurality of signatures to be compared with an input string of characters and including a number of branches of sequential states originating at a root node, wherein each state comprises a state entry including a failure transition and one ... | 03/29/2011 |
| 7916510 | Reformulating regular expressions into architecture-dependent bit groups An apparatus and method of programming a search engine to implement regular expression search operations are disclosed that selectively transform a source regular expression into an equivalent reformulated regular expression in response to a determination of the arc... | 03/29/2011 |
| 7911818 | Content addressable memory having bidirectional lines that support passing read/write data and search data A CAM column structure includes an interface that drives search data to a plurality of CAM cells via a search line pair. The CAM cells are divided into sections, each section including: a set of CAM cells, a bit line pair coupled to the set of CAM cells, a sense amp... | 03/22/2011 |
| 7907432 | Content addressable memory device for simultaneously searching multiple flows A CAM device includes a CAM array coupled to a programmable priority encoding (PPE) logic circuit. The CAM array concurrently compares multiple input data with stored data to generate corresponding match results that are provided to the PPE logic circuit. The PPE lo... | 03/15/2011 |
| 7904642 | Method for combining and storing access control lists A method of minimizing an amount of memory area required to store a plurality of rules associated with one or more access control lists (ACLs) includes selectively combining the plurality of rules into one or more groups depending upon similarities between the entri... | 03/08/2011 |
| 7881125 | Power reduction in a content addressable memory having programmable interconnect structure A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match lin... | 02/01/2011 |
| 7848129 | Dynamically partitioned CAM array A content addressable memory (CAM) device includes a comparand register, a CAM array, and partition logic. The comparand register has inputs to receive a search key, and outputs coupled to the CAM array, which includes a plurality of individually selectable sub-arra... | 12/07/2010 |
| 7876590 | Content addressable memory having selectively interconnected rows of counter circuits A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enabl... | 01/25/2011 |
| 7872346 | Power plane and land pad feature to prevent human metal electrostatic discharge damage An IC package includes an IC die mounted on a substrate that includes an ESD protection structure formed within the substrate to dissipate any charge accumulation associated with the package's no-connect pins resulting from human body model ESD and/or voltage spikes... | 01/18/2011 |
| 7860849 | Optimizing search trees by increasing success size parameter A search tree embodying a plurality of signatures and a number of states each having a failure transition to a fail state and one or more success transitions to next states is optimized by selecting a success size parameter that indicates a maximum number of input c... | 12/28/2010 |
| 7859876 | Method and apparatus for CAM with reduced cross-coupling interference A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed. ... | 12/28/2010 |
| 7856524 | Transposing of bits in input data to form a comparand within a content addressable memory An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a comparand for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the inp... | 12/21/2010 |
| 7853811 | Suspend mode operation for reduced power An integrated circuit (300) includes a suspend circuit that includes a first input to receive a suspend signal, a first output to generate an awake signal, and outputs to provide control signals to various integrated circuit resources. During suspend mode, th... | 12/14/2010 |
| 7844867 | Combined processor access and built in self test in hierarchical memory systems A hierarchical memory includes a plurality of memory blocks, a common access bus coupled to the plurality of memory blocks, and a host bus interface coupled to the common access bus and configured to provide communication between an external host and the plurality o... | 11/30/2010 |
