Did You Know...
...that two musicians were responsible for the invention of color print film? Fascinated by photography, Leopold Godowsky and Leopold Mannes worked together to produce an easy-to-use, practical color film. They worked full time as music teachers and gave concerts while experimenting during their off hours in Mannes' kitchen. Their success earned them full-time, well-paying jobs at Kodak and their efforts resulted in Kodachrome film, which was introduced in 1935.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6564331 | Low power register file A mechanism is provided for reducing the power consumption of a register file by disabling unused register file read ports. A selected entry of the register file is hardwired to zero and the address of the selected entry is driven to the address decoder o... | 05/13/2003 |
| 6564328 | Microprocessor with digital power throttle The present invention provides a digital-based mechanism for adjusting the power consumption in an integrated digital circuit such as a processor. The processor includes one or more functional units and a digital throttle that monitors activity states of ... | 05/13/2003 |
| 6557083 | Memory system for multiple data types A memory system is provided for storing multiple data types. The memory system includes a main memory, a local cache, and a translation unit. The local cache has multiple entries, each of which includes a data field to store data and a status field to ind... | 04/29/2003 |
| 6542966 | Method and apparatus for managing temporal and non-temporal data in a single cache structure A method is provided for managing temporal and non-temporal data in the same cache structure. The temporal or non-temporal character of data targeted by a cache access is determined, and a cache entry for the data is identified. When the targeted data is ... | 04/01/2003 |
| 6438650 | Method and apparatus for processing cache misses A system for processing caches misses includes a request miss buffer, secondary miss logic, and a request identifier buffer. When a request misses in a cache, information characterizing the request is provided to the request miss buffer and the secondary ... | 08/20/2002 |
| 6438682 | Method and apparatus for predicting loop exit branches A loop branch prediction system is provided to predict a final iteration of a loop and resteer an associated fetch module to an appropriate target address. The loop prediction system includes a counter and an end of loop (EOL) module. In one mode, the cou... | 08/20/2002 |
| 6388912 | Quantum magnetic memory A system for storing data on a magnetic medium using spin polarized electron beams is provided. The system includes a source of spin polarized electrons and a storage medium disposed a selected distance from the source. The storage medium has a plurality ... | 05/14/2002 |
| 6321330 | Each iteration array selective loop data prefetch in multiple data width prefetch system using rotating register and parameterization to avoid redundant prefetch The present invention provides a mechanism for prefetching array data efficiently from within a loop. A prefetch instruction is parameterized by a register from a set of rotating registers. On each loop iteration, a prefetch is implemented according to th... | 11/20/2001 |
| 6321327 | Method for setting a bit associated with each component of packed floating-pint operand that is normalized in SIMD operations A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each compone... | 11/20/2001 |
| 6304960 | Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions A system for validating branch predictions for clusters of branch instructions includes an address validation module and a condition validation module. The address validation module determines target addresses for the branches in the cluster. One of the d... | 10/16/2001 |
| 6292886 | Scalar hardware for performing SIMD operations A system for processing SIMD operands in a packed data format includes a scalar FMAC and a vector FMAC coupled to a register file through an operand delivery module. For vector operations, the operand delivery module bit steers a SIMD operand of the packe... | 09/18/2001 |
| 6282636 | Decentralized exception processing system A decentralized exception processing system includes a plurality of local exception units. Each local exception unit is coupled to process local exception signals from one or more processing resources that are proximate to it. Each local exception unit ge... | 08/28/2001 |
| 6272520 | Method for detecting thread switch events A method for detecting thread switch conditions provides first and second scoreboard bits for each register in a register file. The first scoreboard bit associated with a register is set when a load is generated to return data to the register. The second ... | 08/07/2001 |
| 6253315 | Return address predictor that uses branch instructions to track a last valid return address A processor pipeline includes a return stack buffer (RSB) and a top of stack pointer (RSB_TOS) to indicate the status of buffer entries. A copy of the current RSB_TOS (C_TOS) is associated with each branch instruction that is detected at the front end of ... | 06/26/2001 |
| 6240510 | System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions A system is provided for processing concurrently one or more branch instructions in an instruction bundle. The system includes multiple branch execution pipelines, each capable of executing a branch instruction to determine a branch direction, target addr... | 05/29/2001 |
| 6237077 | Instruction template for efficient processing clustered branch instructions A method for processing one or more branch instructions in an instruction bundle is provided. The instructions are ordered in an execution sequence within the bundle, with the branch instructions ordered last in the sequence. The bundled instructions are ... | 05/22/2001 |
| 6233690 | Mechanism for saving power on long latency stalls A method for gating a clock signal to an execution unit on long latency memory stalls monitors a stall signal, a scoreboard (data) hazard signal, a resource hazard signal, and a data return signal. The clock signal is decoupled from the execution unit whe... | 05/15/2001 |
| 6219685 | Method to detect IEEE overflow and underflow conditions A method is disclosed for detecting overflow and underflow conditions using a status register having a main status field and first and second alternate status fields. The first and second alternate status fields are set to chop and wre modes, respectively... | 04/17/2001 |
| 6192515 | Method for software pipelining nested loops A method for software pipelining nested loops combines the inner and outer loops of the nested loop to form a merged loop. One or more operations from the outer loop are activated on selected passes through the merged loop, and the merged loop is software... | 02/20/2001 |
| 6138225 | Address translation system having first and second translation look aside buffers A memory system for providing rapid access to cached data includes a cache, a first TLB that stores address translation entries in a truncated form for fast access to data in the cache, and a second TLB that stores full address translation entries for acc... | 10/24/2000 |
| 6112247 | Network controller for processing status queries A method is provided that allows a networked computer to generate a routable response to a status query without invoking its communication protocol stack. The computer is provided with a network controller that includes query detection and data routing mo... | 08/29/2000 |
| 6111205 | Via pad geometry supporting uniform transmission line structures A connector for coupling high frequency signals between devices includes a substrate having an array of vias for coupling a reference voltage to reference voltage traces that extend along the substrate surface between the devices. Signal traces including ... | 08/29/2000 |
| 6112265 | System for issuing a command to a memory having a reorder module for priority commands and an arbiter tracking address of recently issued command A system and method is provided for enhancing the efficiency with which commands from and initiating device to a resource are processed by the resource. The system includes a command queue, a plurality of command reorder slots coupled to the command queue... | 08/29/2000 |
| 6108781 | Bootstrap processor selection architecture in SMP system A method is provided for selecting a bootstrap processor from among the processors of a multiprocessor system. Each processor has an identity code and each processor that is eligible to serve as the bootstrap processor sends an election message to process... | 08/22/2000 |
| 6084426 | Compensated input receiver with controlled switch-point A compensated CMOS receiver includes an inverter, at least one compensation transistor coupled between a first voltage and the output of the inverter, a comparison circuit coupled to the output of the inverter, and a control circuit coupled to the compari... | 07/04/2000 |
| 6081890 | Method of communication between firmware written for different instruction set architectures A firmware system comprises a legacy firmware module and a native firmware module written for native and legacy instruction set architectures (ISAs), respectively. A data structure is associated with the legacy firmware module to provide access to one or ... | 06/27/2000 |
| 6067643 | Programmable observation system for monitoring the performance of a graphics controller A programmable apparatus is provided that performs real time observation of signals associated with operation of a graphics controller. The apparatus includes a command interface that receives event-monitoring instructions and an observation module that i... | 05/23/2000 |
| 6061265 | Quantum magnetic memory A system for storing data on a magnetic medium using spin polarized electron beams is provided. The system includes a source of spin polarized electrons and a storage medium disposed a selected distance from the source. The storage medium has a plurality ... | 05/09/2000 |
| 6016542 | Detecting long latency pipeline stalls for thread switching An apparatus is provided that operates in conjunction with a processor having registers and associated caches and a memory. A load management module monitors loads that return data to the registers, including bus requests generated in response to loads th... | 01/18/2000 |
| 5991403 | Recoverable cryptographic transformation on YUV data suitable for compressions A method for encoding MPEG compatible video data for subsequent compression comprises detecting a plurality of frames of video data organized as a GOP, generating an encryption key for the GOP, and encrypting the video data using GOP-synchronized substitu... | 11/23/1999 |
| 5963944 | System and method for distributing and indexing computerized documents using independent agents A system is provided in which autonomous agents manage the distribution of data and index information among the nodes of a computer network. The system comprises a network of computer nodes, each of which includes a data store and an agent interface for e... | 10/05/1999 |
| 5933459 | Dual reference voltage input receiver for high speed data transmission A dual reference voltage input receiver comprises a latch, comparison logic for determining the voltage level of a data signal relative to that of first and second reference voltage levels, and selection logic for determining which of the reference voltag... | 08/03/1999 |
| 5904733 | Bootstrap processor selection architecture in SMP systems A method is provided for selecting a bootstrap processor from among the processors of a multiprocessor system. Each processor has an identity code and each processor that is eligible to serve as the bootstrap processor sends an election message to process... | 05/18/1999 |
| 5861893 | System and method for graphics data concurrency and coherency A graphics controller enhances concurrency among multiple pipelines, provides high throughput to graphics resources between 2D and 3D pipelines spawned by an application, and provides low latency for 2D pipelines spawned by an operating system. The graphi... | 01/19/1999 |
| 5842217 | Method for recognizing compound terms in a document A method is provided for identifying compound terms in a document that is represented by a stream of tokens. The stream of document tokens is scanned for an initial term associated with a compound term and a compound term template is accessed when the ini... | 11/24/1998 |
| 5778363 | Method for measuring thresholded relevance of a document to a specified topic A method is provided for specifying the representation of a document and determining the relevance of the document according to an externally defined topic profile. The topic profile includes one or more compound terms having a positive correlation with t... | 07/07/1998 |
| 5774888 | Method for characterizing a document set using evaluation surrogates A method is provided for determining the relevance of a document to one or more topics, each of which is specified by a topic profile. The document is tokenized into a stream of document tokens and compound terms specified in the topic profiles are identi... | 06/30/1998 |
| 5590130 | Bus protocol using separate clocks for arbitration and data transfer A bus system uses separate clocks for arbitration and data transfer. The arbitration clock signal is used for synchronizing bus request and grant events, and the data clock signal is used for synchronizing data transmission and reception. In particular, t... | 12/31/1996 |
| 5563738 | Light transmitting and dispersing filter having low reflectance Multi-layer light filters provide optimized gain control, contrast, and ambient light rejection through the addition of optical layers to a basic refraction light filter. These additional layers allow adjustment of the gain, contrast, and ambient light re... | 10/08/1996 |
| 5551066 | Network link controller for dynamic designation of master nodes A link controller for use in a node of a network includes a digital controller (102) that employs a knowledge-based control program (103). The device and method provide flexible master node designation, automatic installation, configuration and reconfigur... | 08/27/1996 |
