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| Number | Title | Issue Date |
| 6468815 | Overlay radius offset shift engine A method of reducing the effect of placement errors during defect capture and analysis during the manufacture of integrated devices on semiconductor wafers wherein defects from a current layer are evaluated in relation to defects from previous layers afte... | 10/22/2002 |
| 6463171 | Automatic defect resizing tool A method of analyzing and classifying defects on a semiconductor wafer during a semiconductor manufacturing process using an automatic defect resizing tool to accurately measure the sizes of defects.... | 10/08/2002 |
| 6452840 | Feedback method to optimize electric field during channel erase of flash memory devices A method of erasing a flash memory device that improves reliability and reduces the decrease in erase speed. The state of erasure is determined either during an erase phase or a verify phase and the information is fedback to a controller that adjusts the ... | 09/17/2002 |
| 6440789 | Photoresist spacer process simplification to eliminate the standard polysilicon or oxide spacer process for flash memory circuits A method of manufacturing a flash memory semiconductor device that eliminates the step of forming sidewall spacers on n-channel and p-channel transistor gate structures. Resist spacers having a dimension of Gn +2Sn are formed on n-ch... | 08/27/2002 |
| 6423557 | ADC based in-situ destructive analysis selection and methodology therefor A method of inspecting a semiconductor wafer using scanning tools to find defects that occur during the manufacturing process and to the automatic classification, automatic selection of defects that require further analysis, the automatic selection of the... | 07/23/2002 |
| 6424881 | Computer generated recipe selector utilizing defect file information A method of manufacturing semiconductor devices wherein a computer generated list of appropriate review recipes for each layer is available to be used by a review station to review defects on each layer. The most appropriate review recipe is used by the r... | 07/23/2002 |
| 6421574 | Automatic defect classification system based variable sampling plan A method of manufacturing semiconductor devices in which scan data for a current layer of a wafer of a lot being manufactured is compared to previous scan data for previous lots that has been stored in a defect management system. The automatic defect clas... | 07/16/2002 |
| 6395567 | Process control using ideal die data in an optical comparator scanning system A method of detecting defects on dice in semiconductor wafer wherein each dice in a layer is scanned and data from each dice is compared to data collected from an ideal dice obtained from the same level on a pre-production wafer. The data from each dice i... | 05/28/2002 |
| 6387820 | BC13/AR chemistry for metal overetching on a high density plasma etcher A method of manufacturing a semiconductor device by forming layers of materials on a semiconductor substrate and utilizing a series of etch chemistries to remove portions of the layers of materials to form a metal stack. A patterned layer of photoresist d... | 05/14/2002 |
| 6381550 | Method of utilizing fast chip erase to screen endurance rejects A method of utilizing Fast Chip Erase to screen endurance rejects. Multiple sectors in a device are selected and a time necessary to program all cells in the sectors is monitored and if the monitored time exceeds a first time, the device fails. A time nec... | 04/30/2002 |
| 6377898 | Automatic defect classification comparator die selection system A method of analyzing and classifying defects on semiconductor wafers during a semiconductor manufacturing process using a comparator die selector system wherein an automatic defect classification review tool compares defects on a die location with an ide... | 04/23/2002 |
| 6338001 | In line yield prediction using ADC determined kill ratios die health statistics and die stacking A method of manufacturing and inspecting semiconductor devices wherein defects on inspection wafers are tabulated in a stacked defect table wherein a defect table for each layer is generated per die number and a calculated cumulative die health statistic ... | 01/08/2002 |
| 6329273 | Solid-source doping for source/drain to eliminate implant damage A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by minimally oxidizing the gate stack and exposed surface of the substrate, anisotropically etching the layer of oxide from the substrate, forming a doped s... | 12/11/2001 |
| 6303394 | Global cluster pre-classification methodology A method of detecting and pre-classifying cluster type defects in a process for manufacturing semiconductor wafers. At least one inspection wafer is selected from a set of semiconductor wafers being process and the first layer of the set is processed. The... | 10/16/2001 |
| 6297065 | Method to rework device with faulty metal stack layer A method of manufacturing semiconductor wafers wherein a metal layer is formed on a surface of a layer of interlayer dielectric on a partially completed semiconductor wafer and if it is determined that the metal layer is faulty, the faulty metal layer is ... | 10/02/2001 |
| 6293698 | Method for precise temperature sensing and control of semiconductor structures Precise sensing and controlling of temperature during in-situ testing of a structure used in an integrated circuit by fabricating or placing a heat source element adjacent to the structure and by fabricating or placing a temperature sensing element adjace... | 09/25/2001 |
| 6294430 | Nitridization of the pre-ddi screen oxide A flash memory device and a method of manufacturing the flash memory device having high reliability in which a gate stack is formed on a tunnel oxide formed on a substrate and a layer of oxide is formed on the surfaces of the gate stack and exposed surfac... | 09/25/2001 |
| 6291252 | Automatic method to eliminate first-wafer effect A method of manufacturing semiconductor wafers in a processing tool in which it is determined whether the tool has been on idle beyond a predetermined period of time. If the tool has not been on idle beyond the predetermined period of time, a product wafe... | 09/18/2001 |
| 6287968 | Method of defining copper seed layer for selective electroless plating processing A method of manufacturing semiconductor wafers using electroless plating processing. A partially completed semiconductor wafer having trenches and vias formed in a layer of interlayer dielectric has a barrier layer globally formed on the surface of the pa... | 09/11/2001 |
| 6285599 | Decoded source lines to tighten erase Vt distribution A flash memory device and a method to erase the flash memory device having a plurality of memory cells each having a source, a drain, a control gate, wherein the memory cells are organized in rows and columns with a wordline attached to the control gates ... | 09/04/2001 |
| 6284553 | Location dependent automatic defect classification A method of manufacturing semiconductor devices wherein defects on each layer of a semiconductor wafer are determined to be killer or non-killer defects by correlating critical area information on a die with defect size and classification information. The... | 09/04/2001 |
| 6285588 | Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells A method to tighten the threshold voltage distribution curve in a memory device during a negative gate source erase by applying 5 volts to the sources of all the memory cells in the memory device, allowing the drains to float and applying a negative pulse... | 09/04/2001 |
| 6277690 | Elimination of N+ implant from flash technologies by replacement with standard medium-doped-drain (Mdd) implant A method of manufacturing a semiconductor device that eliminates the N+ implant by replacement with resist spacers on n-channel gate structures and a standard Mdd implant. The N+ implant is thereby eliminated from the n-channel trans... | 08/21/2001 |
| 6275415 | Multiple byte channel hot electron programming using ramped gate and source bias voltage A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying vol... | 08/14/2001 |
| 6274396 | Method of manufacturing calibration wafers for determining in-line defect scan tool sensitivity Methods of manufacturing calibration wafers by forming a first layer of a material on a layer of a substrate material. In a first embodiment, calibration spheres are deposited on the first layer of material followed by an etch process that removes exposed... | 08/14/2001 |
| 6272046 | Individual source line to decrease column leakage A flash memory device and a method to read the flash memory device to decrease leakage current during read. The flash memory device has a source line control circuit connected to the sources of memory cells in a row and during read the source line control... | 08/07/2001 |
| 6261960 | High density contacts having rectangular cross-section for dual damascene applications A method of manufacturing a semiconductor device having rectangular cross-sectional interfaces between a conductive line and a conductive via. A first layer of photoresist is patterned to expose portions of the semiconductor device under which conductive ... | 07/17/2001 |
| 6255165 | Nitride plug to reduce gate edge lifting A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by etching a portion of the ends of the layer of tunnel oxide forming cavities, forming silicon nitride plugs in the cavities and forming a layer of oxide o... | 07/03/2001 |
| 6238940 | Intra-tool defect offset system A method of analyzing defects in a semiconductor manufacturing process by removing position offset of a selected scanning tool from the defect location information and adding position offset of a selected review analysis tool. The resulting defect locatio... | 05/29/2001 |
| 6239008 | Method of making a density multiplier for semiconductor device manufacturing A method of manufacturing a semiconductor device with increased density of structures that have at least one dimension less than that provided by the lithography system being used in the manufacturing process.... | 05/29/2001 |
| 6240016 | Method to reduce read gate disturb for flash EEPROM application A method of reading a flash memory (EEPROM) device by applying zero volts to all bitlines and substrate terminal in the flash memory device, a positive voltage of between 4 to 5 volts is applied to the wordline to which the cell being read is attached and... | 05/29/2001 |
| 6238978 | Use of etch to blunt gate corners A method of manufacturing a flash memory device with blunted corners of the floating gate. The blunted corners of the floating gate allow a reduction in the required gate edge lifting that is designed into flash memory design and allows a shortening of th... | 05/29/2001 |
| 6233175 | Self-limiting multi-level programming states A method of programming flash EEPROM devices that provides self-limiting multi-level programming states. Each cell in the flash EEPROM device can be programmed to have one of multiple threshold voltages. Each cell to be programmed has a programming voltag... | 05/15/2001 |
| 6214742 | Post-via tin removal for via resistance improvement A method of manufacturing a semiconductor device having metal structures formed on a first layer of interlayer dielectric, wherein the metal structures have a layer of TiN formed on the surface of the metal structures, a second layer of interlayer dielect... | 04/10/2001 |
| 6204133 | Self-aligned extension junction for reduced gate channel A method of manufacturing a semiconductor device having self-aligned extension junctions and a reduced gate channel length by etching an opening in a layer of phosphoro silicate glass that has been deposited on a substrate. The layer of phosphoro silicate... | 03/20/2001 |
| 6200823 | Method for isolation of optical defect images A method of manufacturing semiconductor devices wherein defect images are isolated from reference images in an optical tool. Each layer of a semiconductor are inspected for defects and identified defect images are subtracted from reference images providin... | 03/13/2001 |
| 6198664 | APDE scheme for flash memory application A method for erasing a flash EEPROM device that includes a plurality of memory cells. The plurality of memory cells is erase verified and an erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again er... | 03/06/2001 |
| 6194259 | Forming retrograde channel profile and shallow LLDD/S-D extensions using nitrogen implants A method of forming a retrograde channel concentration profile in the NMOS region of a semiconductor device and forming a shallow LDD regions in a PMOS region of the semiconductor device. The retrograde channel concentration profile in the NMOS regions is... | 02/27/2001 |
| 6191036 | Use of photoresist focus exposure matrix array as via etch monitor A method of predicting etch efficacy of vias in a semiconductor manufacturing process wherein a photo focus exposure matrix (FEM) array is used as a via etch monitor. The FEM is an array of matrices wherein each array has a different size set of vias. The... | 02/20/2001 |
| 6188609 | Ramped or stepped gate channel erase for flash memory application A method for erasing a flash EEPROM cell by applying a voltage differential between the control gate and the well of the memory cell. The voltage differential can be a ramped or stepped voltage applied to the control gate, a ramped or stepped voltage appl... | 02/13/2001 |
